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[Other] EP1C12Q240C8

Description: FPGA芯片EP1C12Q240C8的完整PDF资料
Platform: | Size: 528197 | Author: allan | Hits:

[Communication] FPGAImplementationof16QAMDemodulator

Description: 描述了一个用于微波传输设备的16QAM接收机解调芯片的FPGA实现,芯片集成了定时恢复、载波恢复和自适应盲判决反馈均衡器(DFE),采用恒模算法(CMA)作为均衡算法。芯片支持高达25M波特的符号速率,在一片EP1C12Q240C8(ALTERA)上实现,即将用于量产的微波传输设备中。
Platform: | Size: 281802 | Author: 萝卜 | Hits:

[Other] EP1C12Q240C8

Description: FPGA芯片EP1C12Q240C8的完整PDF资料-FPGA chip EP1C12Q240C8 a complete PDF information
Platform: | Size: 528384 | Author: allan | Hits:

[Program doc] FPGAImplementationof16QAMDemodulator

Description: 描述了一个用于微波传输设备的16QAM接收机解调芯片的FPGA实现,芯片集成了定时恢复、载波恢复和自适应盲判决反馈均衡器(DFE),采用恒模算法(CMA)作为均衡算法。芯片支持高达25M波特的符号速率,在一片EP1C12Q240C8(ALTERA)上实现,即将用于量产的微波传输设备中。 -Describes a microwave transmission equipment for 16QAM receiver demodulator chip FPGA realization of an integrated chip timing recovery, carrier recovery and blind adaptive decision feedback equalizer (DFE), using constant modulus algorithm (CMA) as the equalization algorithm. Chip supports up to 25M baud symbol rate, in the midst of EP1C12Q240C8 (ALTERA) achieved for the upcoming production of microwave transmission equipment.
Platform: | Size: 281600 | Author: 萝卜 | Hits:

[VHDL-FPGA-Verilog] async_uart

Description: 用verilog写的串口接收发送通信程序，已经在cyclone EP1C12Q240C8调试通过-Serial receiver with verilog send written communication procedures, has been adopted in the cyclone EP1C12Q240C8 debugging
Platform: | Size: 2375680 | Author: 莫少宁 | Hits:

[SCM] EP1C12Q240C8最小系统原理图

Description: EP1C12Q240C8最小系统原理图
Platform: | Size: 86633 | Author: zhengtaiyang | Hits:

[VHDL-FPGA-Verilog] SDRAM_Test5

Description: 基于EP1C12Q240C8的红色飓风二代FPGA开发板的SDRAM测试程序，含有写入和读出FIFO，串口UART,数据发生模块。-Based EP1C12Q240C8 a red hurricane II FPGA development board SDRAM test program, containing written and read FIFO, serial UART, data generation module.
Platform: | Size: 15497216 | Author: linbaoluo | Hits:

[VHDL-FPGA-Verilog] DAC900

Description: 自己写的，FPGA为Cyclone ep1c12q240c8，dac芯片是DAC900。fpga内置ram存储波形数据，发送给dac900产生波形。用VerilogHDL编写。-Write your own, FPGA as Cyclone ep1c12q240c8, dac chip is DAC900. Built-ram fpga store waveform data, waveform generated is sent to dac900. Written VerilogHDL.
Platform: | Size: 27442176 | Author: xiexin | Hits:

[Software Engineering] the-digital-clock

Description: 本设计选用 ALTERA 公司的 EP1C12Q240C8 芯片，利用 VHDL 语言采用自 顶向下的方法在 Quartus Ⅱ环境下完成了数字钟的设计，最后在实验箱上进行测 试。该数字钟包含的功能有计时、显示星期、校时校分、清零、整点报时、音乐 闹铃。-The design uses the silicon chip EP1C12Q240C8 produced by the company of ALTERA. And with the help of VHDL, the design of a digital clock is completed using the top-down approach under Quartus Ⅱ, finally carried out in the SmartSOPC. Functions of the digital clock are: timer, showing day, setting time, resetting, Chime on every hour, and alarm with music.
Platform: | Size: 231424 | Author: 费孝海 | Hits:

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