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[ELanguage] lc2

Description: this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 in a larger model, TOP_LC2 that adds video output. Push buttons reset and single step the processor and a video output display of registers is generated. This state machine VHDL-based model of the LC-2 includes all source files. Currently compiled for a Cyclone EP1C6Q240 FPGA.
Platform: | Size: 43004 | Author: ngzhongsyen | Hits:

[Other resource] ep1c6q240sch

Description: EP1C6Q240 very useful for designer
Platform: | Size: 118775 | Author: hujiansheng | Hits:

[Other resource] Oscillograph

Description: 在EP1C6Q240上实现示波器的逻辑代码.Verilog编写!很好用.调试成功.
Platform: | Size: 1232236 | Author: ZZ | Hits:

[Other resource] reset

Description: 异步复位同步释放的复位信号处理逻辑代码.Verilog编写!很好用.在EP1C6Q240上调试成功.
Platform: | Size: 139489 | Author: ZZ | Hits:

[Other resource] svpwm_full_nios

Description: 这是我毕业设计做的一个SVPWM同步永磁交流电机的控制系统，里面除了一个SVPWM的驱动算法之外，还有一个步进电机的控制器，以及基于QUARTUS7.2的NIOS II控制核心，通过PC的串口可以控制同步永磁交流电机和步进电机进行精确的定位。该系统较复杂，运用的知识也比较多，在SVPWM算法，PID算法，步进电机控制方面，NIOS II的串口编程等都有值得参考的地方。最好使用QUARTUS7.2编译，目标芯片是选用EP1C6Q240
Platform: | Size: 12646564 | Author: 汉武帝 | Hits:

[Embeded Linux] ARM9对FPGA EP1C6Q240进行配置

Description: 在LINUX下使用ARM9对FPGA EP1C6Q240进行配置的例子,其它FPGA也可参考此代码进行配置
Platform: | Size: 35645 | Author: huxiaoping | Hits:

[Documents] ALTERA FPGA特殊管脚说明

Description: FPGA特殊管脚说明-special note
Platform: | Size: 12288 | Author: 王进 | Hits:

[ELanguage] lc2

Description: this a pack include source code for quartus 2. It is an implementation of the LC2. The LC-2 computer is described in Introduction to Computing Systems from Bits & Gates to C & Beyond by Yale Patt and Sanjay Patel, McGraw Hill, 2001. The LC2 model can be run as a simulation or downloaded to the UP3 in a larger model, TOP_LC2 that adds video output. Push buttons reset and single step the processor and a video output display of registers is generated. This state machine VHDL-based model of the LC-2 includes all source files. Currently compiled for a Cyclone EP1C6Q240 FPGA.
Platform: | Size: 43008 | Author: ngzhongsyen | Hits:

[SCM] cyclone

Description: AVR ATMEGA128和FPGA EP1C6Q240C6的开发板，功能强大。-AVR ATMEGA128 and development board FPGA EP1C6Q240C6 and powerful.
Platform: | Size: 1070080 | Author: 文杰 | Hits:

[SCM] ep1c6q240sch

Description: EP1C6Q240 very useful for designer
Platform: | Size: 118784 | Author: hujiansheng | Hits:

[VHDL-FPGA-Verilog] Oscillograph

Description: 在EP1C6Q240上实现示波器的逻辑代码.Verilog编写!很好用.调试成功.-Oscilloscopes EP1C6Q240 achieved in the logic of code. Verilog prepared! Good use. Debugging success.
Platform: | Size: 1231872 | Author: ZZ | Hits:

[VHDL-FPGA-Verilog] reset

Description: 异步复位同步释放的复位信号处理逻辑代码.Verilog编写!很好用.在EP1C6Q240上调试成功.-Asynchronous Reset release synchronous reset signal processing logic code. Verilog prepared! Good use. EP1C6Q240 debugging in the success.
Platform: | Size: 139264 | Author: ZZ | Hits:

[VHDL-FPGA-Verilog] svpwm_full_nios

Description: 这是我毕业设计做的一个SVPWM同步永磁交流电机的控制系统，里面除了一个SVPWM的驱动算法之外，还有一个步进电机的控制器，以及基于QUARTUS7.2的NIOS II控制核心，通过PC的串口可以控制同步永磁交流电机和步进电机进行精确的定位。该系统较复杂，运用的知识也比较多，在SVPWM算法，PID算法，步进电机控制方面，NIOS II的串口编程等都有值得参考的地方。最好使用QUARTUS7.2编译，目标芯片是选用EP1C6Q240-This is my graduation project SVPWM make a permanent magnet AC synchronous motor control system, which apart from a driver SVPWM algorithm, there is a stepper motor controller, as well as QUARTUS7.2 based on the NIOS II control core, through PC serial port can be controlled permanent magnet AC synchronous motor and stepper motor for accurate positioning. The system is more complicated, the use of more knowledge, in the SVPWM algorithm, PID algorithm, stepper motor control, NIOS II serial programming, such as places are worth considering. QUARTUS7.2 compile the best use of the target chip is optional EP1C6Q240
Platform: | Size: 13167616 | Author: 汉武帝 | Hits:

[SCM] ep1c6q240

Description: Altera公司EP1C6Q240开发板电路图，绝对可用。经试验通过。和大家共享-Altera Corporation EP1C6Q240 development board schematics, is absolutely available. Adopted by the pilot. And for all to share
Platform: | Size: 527360 | Author: 鲁凡水 | Hits:

[Software Engineering] EP1C6Q240C6

Description: EP1C6Q240C6开发板原理图，Altera公司的Cyclone系列FPGA—EP1C6Q240-EP1C6Q240C6 development board schematics, Altera' s Cyclone series FPGA-EP1C6Q240
Platform: | Size: 68608 | Author: li | Hits:

[Embeded-SCM Develop] EP1C6Q240-8REG_WR

Description: altera公司的FPGA的一些开发用的VHDL的源代码用于学习-altera INC. develop fpga vhdl source for study and research
Platform: | Size: 529408 | Author: richardz | Hits:

[VHDL-FPGA-Verilog] fpga-pwm

Description: 用verilog 语言写的FPGA子程序，环境是quartus II 7.2 已经在EP1C6Q240上测试过，源码包含仿真文件和仿真结果，本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and simulation results, this procedure can be embedded directly used to do routines.
Platform: | Size: 1163264 | Author: 黄家武 | Hits:

[VHDL-FPGA-Verilog] ira_1

Description: 基于EP1C6Q240 FPGA 核心板的 红外 发射 接收 扩展板 的PCB SCH 的设计文档，红外发射采用PT2248芯片 完成，调制方式 PCM，红外接收采用接收一体头 完成送 FPGA 解码 后 在扩展板的 数码管模块上显示相应内容-EP1C6Q240 FPGA board based on the core of infrared transmitting and receiving expansion board PCB SCH design documents, infrared emission using PT2248 chip, complete, modulation PCM, infrared receiver used to receive the first one to complete the delivery FPGA extension board after decoding the digital control module displays the corresponding content
Platform: | Size: 849920 | Author: 明年此时 | Hits:

[VHDL-FPGA-Verilog] launch

Description: 基于EP1C6Q240 FPGA 核心板的 红外 发射 接收 扩展板 的PCB SCH 的设计文档，红外发射采用PT2248芯片 完成，调制方式 PCM，红外接收采用接收一体头 完成送 FPGA 解码 后 在扩展板的 数码管模块上显示相应内容-EP1C6Q240 FPGA board based on the core of infrared transmitting and receiving expansion board PCB SCH design documents, infrared emission using PT2248 chip, complete, modulation PCM, infrared receiver used to receive the first one to complete the delivery FPGA extension board after decoding the digital control module displays the corresponding content
Platform: | Size: 187392 | Author: 明年此时 | Hits:

[VHDL-FPGA-Verilog] Twister_DDR_SDRAM_Board_Manual

Description: Twister DDR EP1C6Q240 FPGA 开发板 原理图，PCB,BOM-Twister Board Documentation Schematics, PCB and BOM Rev. B
Platform: | Size: 1452032 | Author: SEED | Hits:
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