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[Other resource] clock

Description: 在ACEX EP1K30TC144-3实现了闹钟功能,并能修改定时,和当前时间
Platform: | Size: 524608 | Author: 谢文 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 在ACEX EP1K30TC144-3实现了闹钟功能,并能修改定时,和当前时间-ACEX EP1K30TC144-3 in the realization of the alarm clock function, and can modify from time to time, and the current time
Platform: | Size: 524288 | Author: 谢文 | Hits:

[VHDL-FPGA-Verilog] EP1K30TC144-3

Description: EP1K30TC144-3 PDF。 1k30的FPGA芯片说明文档，我用过1K30一段时间-EP1K30TC144-3 PDF. 1k30 FPGA-chip documentation, I spent some time on 1K30
Platform: | Size: 716800 | Author: Deitel | Hits:

[VHDL-FPGA-Verilog] stop_watch

Description: 实现跑表功能精确度为0.01秒。（使用ACEX1K系列EP1K30TC144-3芯片）-Stopwatch function to achieve an accuracy of 0.01 seconds. (Using ACEX1K series EP1K30TC144-3 chip)
Platform: | Size: 189440 | Author: Haifengqingfu | Hits:

[VHDL-FPGA-Verilog] yi-wei-er-jin-zhi-quan-jia-qi

Description: 一位二进制全加器的源代码及详细WORD文档，maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-A binary full source code and detailed documentation WORD, maxplus software running, pin has been configured, EP1K30TC144-3
Platform: | Size: 133120 | Author: 邱海涛 | Hits:

[VHDL-FPGA-Verilog] shu-kong-fen-pin-qi

Description: 数控分频器的源代码及详细WORD文档，maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-NC divider source code and detailed documentation WORD, maxplus software running, pin has been configured, the chip is EP1K30TC144-3
Platform: | Size: 167936 | Author: 邱海涛 | Hits:

[VHDL-FPGA-Verilog] jia-fa-ji-shu-qi

Description: 含异步清零和同步使能的加法计数器的源代码，用maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-Asynchronous and synchronous cleared with the addition of the counter enable source code, run the software with maxplus Pin has been configured, the chip is EP1K30TC144-3
Platform: | Size: 37888 | Author: 邱海涛 | Hits:

[VHDL-FPGA-Verilog] XU-LIE-JIAN-CE-QI

Description: 用状态机实现序列检测器的源代码，用maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-State of mind achieved with a sequence detector source code, run the software with maxplus Pin has been configured, the chip is EP1K30TC144-3
Platform: | Size: 41984 | Author: 邱海涛 | Hits:

[VHDL-FPGA-Verilog] cai-yang-dian-lu-shi-xian-ADC0809

Description: 用状态机对ADC0809的采样控制电路的实现的源代码，用maxplus软件运行，管脚已配置完成，芯片为EP1K30TC144-3-State machine to achieve ADC0809 sampling control circuit of the source code, run the software with maxplus Pin has been configured, the chip is EP1K30TC144-3
Platform: | Size: 41984 | Author: 邱海涛 | Hits:

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