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Description: 基于VDHL的38译码器的实现与58分频器的实现
FPGA主芯片：CycloneII EP2C35F672C6-Based on VDHL decoder 38 with the divider 58 to achieve the main FPGA chip: CycloneII EP2C35F672C6
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Size: 4599808 |
Author: alan |
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Description: 计算机组织与系统结构实验 用一个74182芯片和四个74181芯片构成一个4位逻辑算数运算器，实现平台为Cyclone II EP2C35F672C6-Computer Organization and Architecture Designing for Performance Experiment
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Size: 265216 |
Author: 欧泽林 |
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Description: FPGA DE2 EP2C35F672C6 开发板原理图、使用手册-FPGA DE2 EP2C35F672C6 development board schematics, user manual
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Size: 56356864 |
Author: yifeng |
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Description: 这是我上电子线路设计课程时自己写的数字钟设计的整个工程.网上下载安装quartus II软件后双击clock.sof打开调试.若软件说没有权限,请删除db文件夹后再试.
文件夹中附带我的实验报告,其中详细讲解了我的设计思路\软件架构\可能出现的问题等等.
调试步骤就不讲了,管脚分配请网友自行完成.
开发板 Altera Cyclone II EP2C35F672C6
软件平台 Quartus II
语言 verilogHDL-These are all the project files and source codes of a digital clock designed on the ALTERA dev. board using Quartus II in verilogHDL when I was taking the electronics design course.
The basic functions are realized here and more details are explained in the attached experiment report. If there are any problems with the codes or debugging, please contact me at zhouyicheng1990@126.com.
Develop Board:
Altera Cyclone II EP2C35F672C6
Software:
Quartus II
Language:
verilogHDL
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Size: 995328 |
Author: needtobestrong |
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Description: 本实验主要练习使用Quartus II 9.1软件进行简单的FPGA 的I/O口实验，实验使用的是DE2开发板，使用芯片为EP2C35F672C6。本次实验的重点是掌握Quartus II 进行系统设计的流程、方法及调试技巧，并对DE2开发板的各个引脚的含义及使用有所了解。-This experiment and practice using the Quartus II 9.1 software is a simple FPGA' s I/O port experiments using a DE2 development board, using the chip EP2C35F672C6. The focus of this experiment is to master the Quartus II design flow, methods, and debugging techniques, and each pin DE2 development board understand the meaning and use.
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Size: 586752 |
Author: xjnkasndx |
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Description: 基于FPGA的单精度浮点数乘法器设计，本文设计了一个基于FPGA的单精度浮点数乘法器。乘法器为五级流水线结构。设计中采用了改进的带偏移量的冗余Booth3算法和跳跃式Wallace树型结构，减少了部分积的数目，缩短了部分积累加的耗时；提出了对尾数定点乘法运算中Wallace树产生的2个伪和采用部分相加的处理方式，有效地提高了的运算速度；并且加入了对特殊值的处理模块，完善了乘法器的功能。单精度浮点数乘法器在Altera DE2开发板上进行了验证，其在Cyclone II EP2C35F672C6器件上的最高工作频率达到212.13 MHz。-FPGA-based single-precision floating-point multiplier design, design of an FPGA-based single-precision floating-point multiplier. Multipliers for the five pipeline structure. Design with improved offset the redundancy Booth3 algorithm and leapfrog Wallace tree structure to reduce the number of partial product, shorten the time-consuming part of the accumulated added on the Wallace tree in the fixed-point multiplication of mantissa two false and part of the additive approach, effectively improving the processing speed and joined the special value of the processing module, and improve the function of the multiplier. Single-precision floating-point multiplier on Altera DE2 development board for verification, its maximum operating frequency of the Cyclone II EP2C35F672C6 device to 212.13 MHz.
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Size: 600064 |
Author: kudding |
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Description: 基于SOPC的串口通讯实验，在DE2开发板上运行通过。芯片为EP2C35F672C6-SOPC-based serial communication experiment, run by the DE2 board. Chip for EP2C35F672C6
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Size: 3072 |
Author: 吴丹 |
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Description: 基于SOPC的定时器实验，包含整个工程，包括硬件板级调试和C代码，在DE2开发板上运行通过。使用芯片为EP2C35F672C6-SOPC-based timer experiments, contains the entire project, including hardware board-level debugging and C code, and run through in the DE2 board. Chip for EP2C35F672C6
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Size: 11494400 |
Author: 吴丹 |
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Description: 一个正弦发生器的设计，应用于EP2C35F672C6开发板，仿真环境为Quartus II 9.1
-A sine generator design, based on EP2C35F672C6 board. Simulated in Quartus II 9.1
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Size: 1272832 |
Author: xipeng |
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Description: 基于Altera公司的开发板DE2--EP2C35F672C6，制作的电子琴，实现do、re、mi、fa、sol、la、xi、do八个音调，并可选择手动或自动播放，其中手动播放可实现存储与回放。并可实现液晶屏对音符的显示。-Development board based on Altera' s DE2- EP2C35F672C6, making organ, realize do, re, mi, fa, sol, la, xi, do eight tones, and can choose manual or automatic playback, which can be achieved manually storage and playback playback. LCD display can be realized on the notes.
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Size: 3143680 |
Author: shuaiwa |
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Description: 本代码为DE2开发板例程源码（EP2C35F672C6），项目基于quartus II 9.0（随板光盘为7.2版本以下，在9.0版以上编译会报错）。本项目实现一个USB画笔功能，通过FPGA控制USB口，USB口接上鼠标，通过XGA口外界显示设备，实现显示设备对鼠标移动轨迹的显示。-In this demonstration, we implement a Paintbrush application by using a USB mouse as the input device.This demonstration uses the device port of the Philips ISP1362 chip and the Nios II processor to implement a USB mouse movement detector. We also implemented a video frame buffer with a VGA controller to perform the real-time image storage and display.
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Size: 2547712 |
Author: chenxin |
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Description: 本代码为Altera DE2开发板例程源码（EP2C35F672C6)，quartus II 9.0以上版本均可编译（随板光盘为quartus II 7.2版在9.0以上版本上编译会报错）。本工程实现SD的音频播放器，即通过FPGA控制SD卡，读取SD的音频文件，通过WM8731进行播放。-In this demonstration we show how to implement an SD Card Music Player on the DE2 board, in
which the music files are stored in an SD card and the board can play the music files via its
CD-quality audio DAC circuits. We use the Nios II processor to read the music data stored in the
SD Card and use the Wolfson WM8731 audio CODEC to play the music.
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Size: 10078208 |
Author: chenxin |
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Description: 本代码为Altera DE2开发板例程源码，（FPGA：EP2C35F672C6）quartus II 9.0以上可以编译（随板源码为7.2以下版本，在9.0以上版本编译会报错）。本代码实现一个音视频播放器TV_BOX。-This demonstration plays video and audio input a DVD player using the VGA output and audio CODEC on the DE2 board. There are two major blocks in the circuit, called I2C_AV_Config and TV_to_VGA. The TV_to_VGA block consists
of the ITU-R 656 Decoder, SDRAM Frame Buffer, YUV422 to YUV444, YCrCb to RGB, and VGA Controller.
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Size: 215040 |
Author: chenxin |
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Description: 用于Altera DE2开发板（EP2C35F672C6)的lcd显示源码-lcd for Altera DE2 development board (EP2C35F672C6) display source
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Size: 565248 |
Author: criss |
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