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[VHDL-FPGA-VerilogEPP

Description: 并口的EPP协议,与外部的FIFO的empty,full信号共同控制数据传输-of EPP parallel port agreement with the external FIFO empty, full common control signal data transmission
Platform: | Size: 1024 | Author: 陈刚 | Hits:

[Communication-MobileEPPTOP

Description: 在altera fpga中实现epp模式的并口通信程序-epp model of parallel in fpga
Platform: | Size: 936960 | Author: chen | Hits:

[VHDL-FPGA-VerilogVHDL_EPP

Description: 用VHDL编写的EPP通信协议,可以同时收发字节-EPP written in VHDL, communication protocol, you can also send and receive bytes
Platform: | Size: 1024 | Author: Roy | Hits:

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