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[Documents] EXCD-1开发板使用手册

Description: 针对XC3S500E设计的开发板，上面介绍了开发板上的各种资源，以及使用方法。
Platform: | Size: 629930 | Author: FPGA_3 | Hits:

[Linux-Unix] EXCD1

Description: 开发板子的管脚约束的定义以及它的内部工作原理，挺不错的-Development board of the pin definition of constraints and its inner workings, very good
Platform: | Size: 629760 | Author: dongchun | Hits:

[Other] paikepdf2

Description: 本文将排课五要素绑定、封装成课元、课栈两个向量，并以二维权值矩阵描述课元 和课栈之间的关联系。 提出了最佳匹配和遗传算法的排课算法，以随机生成的二维数字矩阵来反映课元和 课栈的关联权重，对数字矩阵组处理和最佳匹配得到的匹配偶图组为遗传算法的初始种 群，以排课各种原则的加权和为目标函数，在遗传算子控制下迭代来寻求更优的匹配结 果即使目标函数最小的偶图匹配结构，进而得到满意的排课结果。 提出了关联匹配和禁忌搜索的排课算法，以随机二维数字矩阵描述课元和课栈之问 的关联权重，按照重权优先并根据正确性原则进行约简，获得课元和课栈之间的匹配偶 图。在此基础上，引入禁忌搜索算法，以排课的完备性原则、合理性原则和人性化原则 的加权和为目标函数，以随机二维权值矩阵生成的匹配偶图为初始解，对二维权值矩阵 进行扰动构成搜索邻域，以生成的匹配偶图为禁忌对象，采用全局藐视准则，获得最优 的排课方案。 以Matlab为平台，利用Excd数据库和Mallab的互联实现数据交换，编写了两套 算法的应用程序，通过实例来验证两套排课算法，结果表明两套算法是可行的。-Arranging the five elements of this paper, binding, packaging into a class element, class stack of two vectors and matrices described by two classes per Rights And the relationship between class stack link. Offers the best match and Genetic Algorithm Platoon algorithm to randomly generated two-dimensional figures to reflect the class element and matrix Class stack associated with weight, the digital matrix group received treatment and the best matching group bipartite graph matching the initial kind of genetic algorithm Group to the weighted course arrangement of principles and the objective function, under the control of the genetic operator iteration to seek the better match Results Results even if the objective function structure of the smallest bipartite graph matching, and then Timetabling satisfactory results. Match the proposed association Timetabling algorithm and tabu search, a random two-dimensional digital matrix element and the class description class stack of Q
Platform: | Size: 1812480 | Author: 张林杰 | Hits:

[VHDL-FPGA-Verilog] EXCD-1

Description: 这是基于XILINX公司主推的一款性价比十分高的FPGA开发办的资料原理图，希望对大家有帮助-This is based on the company' s main push of a XILINX very high cost FPGA development office schematic information, we want to help
Platform: | Size: 140288 | Author: zhanghan | Hits:

[VHDL-FPGA-Verilog] PWMcore

Description: 基于xilinx FPGA软核microblaze编写的PWM波产生IP核，在EXCD开发板上调试通过，内附UCF文件和说明-it s an IP core based on microblaze,it can produce pwm wave.
Platform: | Size: 17408 | Author: JK | Hits:

[VHDL-FPGA-Verilog] SEGcore

Description: 基于MICROBLAZE的数码管扫描IP核，在EXCD开发板上调试通过，可移植至其他开发板-An IP core based on microblaze,it is used for leds scanning
Platform: | Size: 17408 | Author: JK | Hits:

[VHDL-FPGA-Verilog] testps2

Description: 基于xilinx excd开发板的PS/2键盘计算器，能完成1位数据的加减乘除，功能可扩展-it s a ps/2 keyboard caculator
Platform: | Size: 4684800 | Author: JK | Hits:

[VHDL-FPGA-Verilog] xlinx_ise_excd1_edk_flash_program

Description: 这是一个网友向我提问如何实现EXCD1开发板的FLASH管理，我编写的一个Xilinx的EDK设计包括设计步骤说明，没有经过实际测试，希望在实际使用中有问题的网友与我讨论。谢谢！-This is a friends asked me how EXCD1 development board FLASH management, I prepared a Xilinx s EDK design and including the design steps that, without actual test, I hope there are problems in the actual use of the discussion with my friends. Thank you!
Platform: | Size: 6530048 | Author: YongZhiLi | Hits:

[VHDL-FPGA-Verilog] IS61WV51216BLL

Description: 备注：使用的是VeriLog HDL语言 软件环境xilinx ISE 10.1，硬件：高教仪EXCD-1FPGA电路板。FPGA信号：spartan-3e . 功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写，通过串口发送到上位机上，使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher Miriam EXCD-1FPGA circuit boards. FPGA Signal: spartan-3e. Write functional hardware description language implementation of on-board peripherals SRAM IS61WV51216BLL FPGA to read and write, sent to the host computer through the serial port, use the serial Assistant displays the data read.
Platform: | Size: 5120 | Author: 李钿 | Hits:

[VHDL-FPGA-Verilog] gj-2s

Description: 基于赛灵思EXCD-1的FPGA开发板，使用ISE10.1开发环境，使用VHDL语言编写，功能为计算输入方波的频率。输入方波，输出方波的频率，用数码管显示，每2s更新一次。管脚配置见工程。-Based on the FPGA Xilinx EXCD-1 development board, using ISE10.1 development environment, using the VHDL language, functions for calculating the frequency of the input square wave. Enter the square wave output square wave frequency, with digital display, updated once every 2s. Pin configuration, see projects.
Platform: | Size: 873472 | Author: 希望 | Hits:

[VHDL-FPGA-Verilog] clock

Description: XPS做时钟的配置过程基于EXCD-1开发板,其实是基于xilinx的ISE来开发的，但是开发环境没有这个就这能选VHDL，另外是verilog的，呵呵。希望大家能够真正用上，挺好的“基于ISE的时钟”-XPS to do the configuration process is based on the clock EXCD-1 development board, in fact, is based on the xilinx the ISE to develop, but not the development environment that can be selected to VHDL, the other is verilog, huh, huh. Hope that we can really spend, very good " based on ISE' s Clock"
Platform: | Size: 2779136 | Author: 江源 | Hits:

[VHDL-FPGA-Verilog] EXCD1yuanlitu

Description: EXCD-1 Spartan 3E开发板原理图-EXCD-1 Spartan 3E development board schematics
Platform: | Size: 115712 | Author: hhq | Hits:

[VHDL-FPGA-Verilog] EXCD1shouce-(1)

Description: EXCD-1 Spartan3E 开发板手册-EXCD-1 Spartan3E Development Board Manual
Platform: | Size: 629760 | Author: hhq | Hits:

[VHDL-FPGA-Verilog] build-a-simple-project

Description: EXCD-1可编程片上系统 实验例程EDK部分 之建立一个简单的工程 -EXCD-1 programmable system on chip test routine part of the EDK project to build a simple
Platform: | Size: 3959808 | Author: 魏帅 | Hits:

[VHDL-FPGA-Verilog] add-an-IP-to-EDK-hardware-design

Description: EXCD-1 可编程片上系统 实验例程中的EDK部分 功能：添加一个IP 到硬件设计-EXCD-1 programmable system on chip experimental part of the routine to add an IP to EDK hardware design
Platform: | Size: 4186112 | Author: 魏帅 | Hits:

[VHDL-FPGA-Verilog] Custom-IP-to-a-hardware-design

Description: EXCD-1 可编程片上系统 实验例程 EDK部分 功能：定制一个IP 到硬件设计-EXCD-1 programmable system on chip test routines EDK some of the features: a custom IP to hardware design
Platform: | Size: 4279296 | Author: 魏帅 | Hits:

[VHDL-FPGA-Verilog] Write-applications

Description: EXCD-1 可编程片上系统 实验例程 EDK部分 功能：编写应用程序-EXCD-1 Programmable System on Chip experiments EDK part of the routine functions: to write applications
Platform: | Size: 4444160 | Author: 魏帅 | Hits:

[VHDL-FPGA-Verilog] CHIPSCOPE-to-use-the-SDK-tools-

Description: EXCD-1 可编程片上系统 实验例程 EDK部分 功能：使用SDK 工具和CHIPSCOPE 进行软硬件协同调试-CHIPSCOPE to use the SDK tools and hardware and software co-debugging
Platform: | Size: 7319552 | Author: 魏帅 | Hits:

[VHDL-FPGA-Verilog] shumaguanxianshisheji

Description: 七段数码管显示设计 EXCD-1 可编程片上系统开发板 使用VHDL 语言编写7 段数码管显示程序-Seven segment display design EXCD-1 programmable system on chip development board using VHDL language 7-segment display program
Platform: | Size: 1024 | Author: 杨明 | Hits:

[VHDL-FPGA-Verilog] ISE_lab14_traffic

Description: excd板子上交通灯的实现 数码管实时显示 限于excd学习板-excd-1 traffic led
Platform: | Size: 518144 | Author: alex | Hits:
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