Description: fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim Platform: |
Size: 7812 |
Author:zqh |
Hits:
Description: FPGA加密的方法，对于那些需要加密自己的vhdl源代码的人来说，很有用-FPGA encryption methods for those who need to encrypt their VHDL source code in a way, very useful Platform: |
Size: 187392 |
Author:陶伟炯 |
Hits:
Description: fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim Platform: |
Size: 7168 |
Author:zqh |
Hits:
Description: VHDL 的FFT 1024点源码。既有VHDL 的，也有Verlog的。比较好用。占用资源少-VHDL source code of the FFT 1024 points. Both VHDL and there are also some of the Verlog. Comparison of ease of use. Occupy less resources Platform: |
Size: 37888 |
Author:张加良 |
Hits:
Description: fft源代码，希望对大家有用，谢谢
fft源代码，希望对大家有用，-fft source code, in the hope that useful to everybody, thank you fft source code, in the hope that useful to everybody, Platform: |
Size: 1024 |
Author:111 |
Hits:
Description: verilog语言实在点变换DFT源代码，可以配合软核或者其他CPU进行综合FFT变换，也可以单独使用生成module！-verilog language is point FFT transform source code, can tie in with the soft-core CPU, or other integrated FFT transform, it can be used to generate module! Platform: |
Size: 1024 |
Author:刘庆 |
Hits:
Description: FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.
Platform: |
Size: 6144 |
Author:Jayesh |
Hits:
Description: This a code for FFT in VHDL, Verilog & C
Source: OpenCores.org-This is a code for FFT in VHDL, Verilog & C
Source: OpenCores.org Platform: |
Size: 3125248 |
Author:Kiran |
Hits:
Search - FFT source code in vhdl