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[assembly language] saa7111_2

Description: 使用Altera芯片实现对4个SAA7111A视频A/D芯片的采集控制，将图像数据存入同步FIFO-AL422B-use Altera chip to 4 SAA7111A Video A/D chip to control the collection, image data are stored in synchronous FIFO- AL422B
Platform: | Size: 1024 | Author: 古韦剑 | Hits:

[VHDL-FPGA-Verilog] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2048 | Author: nick | Hits:

[VHDL-FPGA-Verilog] Audio_DAC_FIFO

Description: altera的ip核，在sopcbuilder中添加后，在niosII IDE中可以用一条语句实现，音频解码的输出。-altera
Platform: | Size: 15360 | Author: 朱峰 | Hits:

[VHDL-FPGA-Verilog] 16550

Description: UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。-UART16550 compatible serial communication controller, Verilog language description, the use of Altera Cyclone series FPGA chip integrated, as part of the use of FIFO to the internal resources to achieve. Projects have been in a successful application, is hereby introduced.
Platform: | Size: 10240 | Author: David.Mr.Liu | Hits:

[VHDL-FPGA-Verilog] Fifo

Description: 一个FIFO源代码，基于Altera FPGA-A FIFO source code, based on Altera FPGA
Platform: | Size: 1024 | Author: jiashengwen | Hits:

[VHDL-FPGA-Verilog] SOPC_Builder

Description: SOPC架构建立实例，针对altera公司的DE2开发板，其他开发系统也可以用-based FPGA , SOPC construct experiment
Platform: | Size: 2323456 | Author: zhaoqian | Hits:

[VHDL-FPGA-Verilog] de2_lcm_ccd_sram

Description: 这是altera公司DE2的lcm-ccd-sram的代码，希望对大家编写有用-this code based on the altera DE2 board
Platform: | Size: 918528 | Author: ningning | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现先进先出的队列。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 Development Board to achieve FIFO queue.
Platform: | Size: 164864 | Author: Daisy | Hits:

[VHDL-FPGA-Verilog] Altera_FIFO

Description: Altera FIFO的多极级联，实现多个FIFO之间的数据传输。-Altera FIFO multi-polar cascading between multiple FIFO data transmission.
Platform: | Size: 3072 | Author: Robert | Hits:

[Communication-Mobile] asynchronous_fifo

Description: Fully asynchronous fifo for Altera devices.
Platform: | Size: 2048 | Author: kkris | Hits:

[Software Engineering] generic_fifos

Description: Generic FIFO for use with both xilinx and altera
Platform: | Size: 39936 | Author: ufz | Hits:

[VHDL-FPGA-Verilog] altera_fifo

Description: altera 公司的 FIFO 文档，这是设计同步或异步FIFO的重要文档-altera s FIFO document
Platform: | Size: 294912 | Author: liuminghua | Hits:

[VHDL-FPGA-Verilog] qts_qii55002

Description: ALTERA on chip fifo. this document is from altera. good resouce
Platform: | Size: 135168 | Author: 李林 | Hits:

[VHDL-FPGA-Verilog] dcfifo_design_example

Description: ALTERA发布的内部FIFO读写示例，很有参考价值，对初学者会有一定的帮助-ALTERA' s internal FIFO read and write examples of great reference value, there will be some help for beginners
Platform: | Size: 33792 | Author: 吕飞 | Hits:

[VHDL-FPGA-Verilog] test_sdram

Description: 对SDRAM进行读写，工程内部分为PLL以及复位处理模块、写SDRAM逻辑模块、读SDRAM逻辑模块、SDRAM读写封装模块、读写缓存FIFO模块、串口发生模块等。工程基于altera的Quartus II 10.1进行设计，使用更高版本的软件均可。-SDRAM read and write for the project is divided into the internal PLL and reset processing module, SDRAM write logic block, logic block read SDRAM, SDRAM modules package to read and write, read and write buffer FIFO module, serial module occurs. Altera-based engineering design of the Quartus II 10.1, the software can be used later.
Platform: | Size: 3128320 | Author: | Hits:

[VHDL-FPGA-Verilog] ram_fifo

Description: Altera RAM FIFOIP核，实现对FIFO的读写，对满信号和空信号进行判断.-altera ram fifo ip core
Platform: | Size: 3232768 | Author: xuguo | Hits:

[VHDL-FPGA-Verilog] ram-and-fifo

Description: ALTERA公司的一些关于RAM，FIFO等IP核的技术文档，对用到IP核存储设备的读者很有用！-ALTERA Company RAM, FIFO IP core technical documentation, readers used IP core storage devices useful!
Platform: | Size: 920576 | Author: 刘宁 | Hits:

[File Format] Altera-FIFO

Description: 介绍了Altera的FPGA的FIFO的功能与介绍-Introduction of Altera' s FPGA capabilities with the introduction of the FIFO
Platform: | Size: 701440 | Author: 王兵兵 | Hits:

[SCM] fifo

Description: 利用stm32f407作为测试板，利用IO和精确的延时（这个延时方式任意）来模拟FIFO时序来达到和FPGA的FIFO模块进行通信。测试时用的是Altera的FPGA的FIFO模块。-Stm32f407 use as a test board, the use of IO and accurate delay (the delay in any way) to simulate FIFO timing to achieve and FPGA FIFO module to communicate. When the test is used in Altera' s FPGA' s FIFO module.
Platform: | Size: 1024 | Author: 龙鸿峰 | Hits:

[VHDL-FPGA-Verilog] CCD_Array

Description: Interface TCD1209DG with Altera FPGA and transfer image data to PC via USB using USB FX2 Slave FIFO mode, Only FPGA code included.
Platform: | Size: 3320832 | Author: muralidh | Hits:
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