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Description: DSP做的视频处理系统中FIFO问题解答-DSP video processing system FIFO Questions
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Size: 3223 |
Author: 陈旭 |
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Description: Wavelets have widely been used in many signal and image processing applications. In this paper, a new
serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet
transform, which is realised using some FIFO memory modules implementing a pixel-level pipeline
architecture to compress and decompress images. The real filter calculation over 4 · 4 window blocks is
done using a tree of carry save adders to ensure the high speed processing required for many applications.
The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis
reveals that the proposed architecture, implemented using current VLSI technologies, can process a
video stream in real time.-Wavelets have been widely used in many sign al and image processing applications. In this p aper. a new serial-parallel architecture for wavele t-based image compression is introduced. It is based on a 4-tap wavelet transform. which is realized using some FIFO memory module 's implementing a pixel-level pipeline archite cture to compress and decompress images. The're al filter calculation over 4 blocks window is done using a tree of carry save adders to ensure t he high speed processing required for many appl ications. The details of implementing both com pressor decompressor and sub-systems are give n. The primarily analysis reveals that the prop osed architecture, VLSI implemented using current technologies, can process a video stream in real time.
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Size: 2837459 |
Author: sdfafaf |
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Description: DSP做的视频处理系统中FIFO问题解答-DSP video processing system FIFO Questions
Platform: |
Size: 3072 |
Author: 陈旭 |
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Description: Wavelets have widely been used in many signal and image processing applications. In this paper, a new
serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet
transform, which is realised using some FIFO memory modules implementing a pixel-level pipeline
architecture to compress and decompress images. The real filter calculation over 4 · 4 window blocks is
done using a tree of carry save adders to ensure the high speed processing required for many applications.
The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis
reveals that the proposed architecture, implemented using current VLSI technologies, can process a
video stream in real time.-Wavelets have been widely used in many sign al and image processing applications. In this p aper. a new serial-parallel architecture for wavele t-based image compression is introduced. It is based on a 4-tap wavelet transform. which is realized using some FIFO memory module 's implementing a pixel-level pipeline archite cture to compress and decompress images. The're al filter calculation over 4 blocks window is done using a tree of carry save adders to ensure t he high speed processing required for many appl ications. The details of implementing both com pressor decompressor and sub-systems are give n. The primarily analysis reveals that the prop osed architecture, VLSI implemented using current technologies, can process a video stream in real time.
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Size: 2837504 |
Author: sdfafaf |
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Description: 提出了利用fifo,实现dsp之间的高速、实时、可靠的数据传输,介绍了fifo原理及性能特点，详细阐述了系统的硬
件接口电路及软件设计。
-the use fifo achieve dsp between the high-speed, real-time, reliable data transmission, fifo on the principles and performance characteristics of a detailed description of the hardware and software interface circuit design.
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Size: 87040 |
Author: 权溪 |
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Description: 重点介绍了DSP与FIFO的数据传输、DSP与USB的接口电路。解决了一般情况下系统无法做到的用线阵CCD实现二维图像信号复原的问题
-focus on the DSP and FIFO data transmission, DSP and USB interface circuit. Solve the system under normal circumstances can not do in line with two-dimensional CCD image signals of recovery
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Size: 134144 |
Author: 权溪 |
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Description: XILINX的FPGA实现的双口ram源码，可作为dsp\SDRAM和pci桥接作用，可直接使用，实际工程通过。-XILINX FPGA Implementation of the dual-port ram source, as dsp \ SDRAM and pci bridge, and can be used directly, through practical projects.
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Size: 19456 |
Author: 朱效志 |
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Description: DSP通过EMIF接口与外部FIFO通信并实现IQ调制功能-DSP through the EMIF interface with external FIFO communication and realize IQ modulation function
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Size: 4096 |
Author: 汤玉宇 |
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Description: SD卡和AIC23数字音频输出实验, FreeDev Audio Dsp Board采用了TI公司的TVL320AIC23
1、控制接口使用I2C，Quartus中将CS置低（器件地址0011010）。 2、数字音频接口使用了组件FreeDev_aic23,有三种测试和应用
模式，中断结合DMA方式能在NIOS II中采集和发送数据。中断信号 产生于模块中FIFO缓冲区的半满信号，读取数据端口自动清除中断
请求信号。 3、I2C IP 和FreeDev_aic23 IP分别在Quartus 工程目录中 4、SD卡读写通过SD_DAT0、SD_CLK、SD_CMD三个PIO信号线用软件 控制时序。 5、该范例读SD卡数据，通过DMA将Buffer数据送到FreeDev_aic23的
FIFO中实现数据播放。 6、SD卡中的数据必须是以48K*16bit保存的采样数据。数据可以通过SD读卡器写入。
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Size: 13312 |
Author: HuFengzhang |
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Description: 基于高速数字信号处理器(DSP) 和大规模现场可编程门阵列( FPGA) ,成功地研制了小型
化、低功耗的实时视频采集、处理和显示平台. 其中的DSP 负责图像处理,其外围的全部数字逻辑功能都集成在一片FPGA 内,包括高速视频流FIFO、同步时序产生与控制、接口逻辑转换和对视频编/ 解码器进行设置的I2 C 控制核等. 通过增大FIFO 位宽、提高传输带宽,降低了占用EMIF 总线的时间 利用数字延迟锁相环逻辑,提高了显示接口时序控制精度. 系统软件由驱动层、管理层和应用层组成,使得硬件管理与算法程序设计彼此分离,并能协同工作. 系统中的图像缓冲区采用了
三帧的配置方案,使得该平台最终具有对PAL/ N TSC 两种制式的全分辨率彩色复合视频信号进行实时采集、显示和处理的能力.-Based on high-speed digital signal processor (DSP) and large-scale field programmable gate array (FPGA), successfully developed a smaller, low-power real-time video capture, processing and display platform. One of the DSP is responsible for image processing, all its external digital logic functions are integrated in a FPGA, including high-speed video streaming FIFO, synchronous sequential generate and control, conversion and interface logic for video encoder/decoder to set up the control of nuclear and other I2 C. through increased FIFO bit width, increase the transmission bandwidth, reducing the time occupied by EMIF bus delay phase-locked loop using digital logic,
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Size: 546816 |
Author: John |
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Description: it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.
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Size: 31744 |
Author: yasir ateeq |
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Description: 实现FPGA通过EMIF总线给DSP定期发送数据的功能-FPGA implementation through the EMIF bus regularly send data to the DSP function
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Size: 1480704 |
Author: 徐成发 |
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Description: DSP uart窗口通信中的一种通信格式，FIFO模式的一个小程序-dsp serial communication uart communication first in first out-FIFO mode
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Size: 4096 |
Author: luoxin |
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Description: DSP上实现 软件FIFO队列 提高SCI的数据缓冲能力-DSP to achieve the software improve the SCI data FIFO queue buffering capacity
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Size: 5120 |
Author: 王易龙 |
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Description: FIFO circular buffer for DSP
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Size: 2048 |
Author: slimx2 |
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Description: 包括定时器、SPI、SDRAM、Flash、FIFO等程序，均调试通过-SPI\SDRAM\Flash\FIFO\timer for DSP6713
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Size: 916480 |
Author: HYD |
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Description: DSP2812串口通信编程，利用FIFO中断接收数据以及利用查询方式发送数据-TMS320F2812SCI code
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Size: 389120 |
Author: 黄晓军 |
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Description: 近年来，随着DSP的快速发展，被广泛的应用于图像处理及目标定位[11][13][21]上，极大地提高图像处理的实时性。DSP主要用来实现扩展算法和数字信号处理的功能，其最典型的用途是实现数字图像处理算法。DSP芯片内采用大容量的SRAM作为系统的高速缓存，高达64位的数据总线带宽。在片外采用了目前流行的SDRAM、DDR2等高速大容量存储器的无缝连接，同时还支持SRAM、FIFO等各种类型的存储器，大大提高了图像的存储容量及速度。-In recent years, with the rapid development of DSP, has been widely used in image processing and target location [11] [13] [21], and greatly improve the image processing in real time. Mainly used to implement DSP algorithms and digital signal processing expansion of the function, the most typical use digital image processing algorithms. DSP chip with large-capacity SRAM cache as a system, up to 64-bit data bus bandwidth. Chip used in the popular SDRAM, DDR2 memory and other high-speed large-capacity seamless connection, and also supports SRAM, FIFO, and other types of memory, greatly improving the image storage capacity and speed.
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Size: 261120 |
Author: 侯国强 |
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Description: 近年来，随着DSP的快速发展，被广泛的应用于图像处理及目标定位[11][13][21]上，极大地提高图像处理的实时性。DSP主要用来实现扩展算法和数字信号处理的功能，其最典型的用途是实现数字图像处理算法。DSP芯片内采用大容量的SRAM作为系统的高速缓存，高达64位的数据总线带宽。在片外采用了目前流行的SDRAM、DDR2等高速大容量存储器的无缝连接，同时还支持SRAM、FIFO等各种类型的存储器，大大提高了图像的存储容量及速度。-In recent years, with the rapid development of DSP, has been widely used in image processing and target location [11] [13] [21], and greatly improve the image processing in real time. Mainly used to implement DSP algorithms and digital signal processing expansion of the function, the most typical use digital image processing algorithms. DSP chip with large-capacity SRAM cache as a system, up to 64-bit data bus bandwidth. Chip used in the popular SDRAM, DDR2 memory and other high-speed large-capacity seamless connection, and also supports SRAM, FIFO, and other types of memory, greatly improving the image storage capacity and speed.
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Size: 1499136 |
Author: 侯国强 |
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Description: 本文档提供了DSP对FPGA中的FIFO的读写时序以及编程思路，供大家参考。(This document provides DSP on the FPGA FIFO read and write timing and programming ideas for your reference.)
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Size: 987136 |
Author: wangxiaobei
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