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[File Format] 一种基于FPGA的并行流水线FIR滤波器结构 DL : 0: 这是我看到的一些资料，希望与大家分享。也许这对您用处不大，但是我的一份诚意。-this is that I see some of the information and hope to share with you all. This may be less useful to you, but my sincerity.
Update : 2025-03-14 Size : 194kb Publisher : yin
[VHDL-FPGA-Verilog] vhdlsynth_fft DL : 0: FFT的VHDL源代码的实现与仿真结果，经过FPGA源型机验证，已通过-FFT VHDL source code and the realization of simulation results, after FPGA source aircraft certification, have passed
Update : 2025-03-14 Size : 61kb Publisher :
[STL] FIRDATA DL : 0: FIR 数字滤波器分布式算法及其FPGA实现-FIR digital filter algorithms and FPGA
Update : 2025-03-14 Size : 30kb Publisher : ankerbb
[VHDL-FPGA-Verilog] firfpga DL : 0: 在利用FPGA实现数字信号处理方面，分布式算法发挥着关键作用，与传统的乘积-积结构相比，具有并行处理的高效性特点。详细研究了基于FPGA、采用分布式算法实现FIR数字滤波器的原理和方法，并通过Xilinx ISE在Modelsim下进行了仿真。 -FPGA using digital signal processing, distributed algorithm plays a key role with the traditional product-plot structure compared with the efficient parallel processing features. Based on a detailed study of the FPGA, using distributed algorithm FIR digital filter method and the principle, and through the Xilinx ISE under the Modelsim simulation.
Update : 2025-03-14 Size : 223kb Publisher : yaoming
[VHDL-FPGA-Verilog] fir DL : 0: FIR数字滤波器程序，采用vhdl编写，可用于FPGA电路-FIR digital filter procedure for the preparation of VHDL can be used in FPGA circuit
Update : 2025-03-14 Size : 169kb Publisher : zhao onely
[VHDL-FPGA-Verilog] FIR DL : 0: 此文件包括FIR滤波器的设计对EDA的介绍，以及用VHDL语言实现FIR滤波器的FPGA实现-This document includes the design of FIR filters on the EDA
Update : 2025-03-14 Size : 2.41mb Publisher : solor1985
[VHDL-FPGA-Verilog] fpga DL : 0: fpga功能实现有限字长响应FIR 用verilog编写-FPGA functionality in response to the realization of finite word-length FIR prepared using Verilog
Update : 2025-03-14 Size : 136kb Publisher : 吴务
[VHDL-FPGA-Verilog] FIR DL : 0: ＦＰＧＡ实现数字滤波器，基于硬件描述语言ＶＥＲＩＬＯＧ　ＨＤＬ，顶层文件ＦＩＲ．Ｖ-FPGA realization of digital filters, based on the hardware description language VERILOG HDL, the top-level file FIR. V
Update : 2025-03-14 Size : 5kb Publisher : YP
[VHDL-FPGA-Verilog] FIR DL : 0: FIR数字滤波器分布式算法的原理及FPGA实现-Distributed Arithmetic FIR digital filter FPGA Principle and realize
Update : 2025-03-14 Size : 585kb Publisher : 王杰
[Documents] fir DL : 0: 线性相位FIR滤波器（17阶）的VHDL语言设计功能很强大，很好用-Linear phase FIR filter (17 bands) of the VHDL language design features a very powerful, very good use
Update : 2025-03-14 Size : 145kb Publisher : jingjing
[VHDL-FPGA-Verilog] fpga DL : 0: On a distributed algorithm based on FPGA pipelined FIR filter of the article.
Update : 2025-03-14 Size : 1.25mb Publisher : haha
[VHDL-FPGA-Verilog] FIR DL : 0: FIR结构数字滤波器，64阶。在Altera FPGA上验证通过-FIR digital filter structure, 64 bands. Verified by the Altera FPGA on the
Update : 2025-03-14 Size : 5kb Publisher : 蓝晶
[VHDL-FPGA-Verilog] Xilinx-FIR DL : 0: 基于Xilinx FPGA实现的系数可装载数字滤波器源代码-Configurable Digital Filter Based on FPGA (using Verilog under Matlab 2008a)
Update : 2025-03-14 Size : 2.95mb Publisher : 胡文静
[VHDL-FPGA-Verilog] FIR-filter-using-fpga-design DL : 0: 基于FPGA的高阶FIR滤波器设计4有matlab设计步骤 4.3更详细第六章量化系数实例-FIR using FPGA ，QuartusII software
Update : 2025-03-14 Size : 4.33mb Publisher : 星空心晴之夏
[VHDL-FPGA-Verilog] fir-filter-design-using-fpga-with-MAX-Plus2 DL : 1: 基于FPGA的高阶FIR滤波器设计用max-plus　－II软件仿真-fir filter using fpga with max-plusII
Update : 2025-03-14 Size : 2.23mb Publisher : 星空心晴之夏
[VHDL-FPGA-Verilog] fir DL : 0: FIR Filter Fits in an FPGA using a Bit Serial Approach
Update : 2025-03-14 Size : 62kb Publisher : mm
[VHDL-FPGA-Verilog] fir DL : 0: FPGA实现的FIR滤波器，很好的参考资料！-FPGA implementation of FIR filters, a very good reference!
Update : 2025-03-14 Size : 383kb Publisher : 吴锦干
[VHDL-FPGA-Verilog] FIR-FPGA DL : 0: 一种基于FPGA的高效FIR滤波器的设计与实现 -An efficient FIR filter based on FPGA of design and implementation
Update : 2025-03-14 Size : 248kb Publisher : 陈小子
[VHDL-FPGA-Verilog] DA-FIR-FPGA DL : 0: 详细介绍了分布式算法FIR的设计，对于用FPGA实现FIR的设计具有指导意义。来自华中科大。-Detailed design of a distributed algorithm FIR, FPGA implementation for the FIR design with a guide. From HUST.
Update : 2025-03-14 Size : 284kb Publisher : ye
[VHDL-FPGA-Verilog] fir filter design DL : 0: FIR FILTER DESIGN IN VERILOG ON FPGA
Update : 2025-03-14 Size : 18kb Publisher : GIRISH

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