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[Other resource] firmatlab

Description: fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
Platform: | Size: 6507 | Author: zqh | Hits:

[VHDL-FPGA-Verilog] FIR低通滤波器部分模块

Description: 一个FIR低通滤波器,最小阻带衰减-30db,带内波动小于1db．用MAXPLUS2设计与仿真。-This is a FIR LPF, with-30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.
Platform: | Size: 5120 | Author: 吴健宇 | Hits:

[VHDL-FPGA-Verilog] firmatlab

Description: fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
Platform: | Size: 6144 | Author: zqh | Hits:

[Other] m_cov_cul03_unmodule_precise

Description: 该程序用以对m序列码的调制在负dB情况下解调的仿真，是对基带信号的调制-procedures for the right sequence code m in the negative dB modulation of the demodulation simulation of the base band signal modulation
Platform: | Size: 1024 | Author: 孙晓东 | Hits:

[matlab] vhdl_fir

Description: 在matlab仿真的基础上，用maxplus2实现等波纹法的程序代码-In matlab simulation, based on the use of such corrugated maxplus2 realize law code
Platform: | Size: 5120 | Author: 王娟芳 | Hits:

[VHDL-FPGA-Verilog] DA_FIR

Description: 基于分布式算法的FPGA实现的FIR滤波器源码，VHDL语言编写的，下载工程文件后可直接在QuartusII7.0上运行。-Based on Distributed algorithms realize the FIR filter FPGA source code, VHDL language, download the project file can be run directly in QuartusII7.0.
Platform: | Size: 531456 | Author: CH | Hits:

[Other] VerilogHDL

Description: 本文主要分析了FIR数字滤波器的基本结构和硬件构成特点,简要介绍了FIR滤波器实现的方式优缺点 结合Altera公司的Stratix系列产品的特点,以一个基于MAC的8阶FIR数字滤波器的设计为例,给出了使用Verilog硬件描述语言进行数字逻辑设计的过程和方法,并且在QuartusⅡ的集成开发环境下编写HDL代码,进行综合 利用QuartusⅡ内部的仿真器对设计做脉冲响应仿真和验证。-This paper analyzes the FIR digital filter structure and the basic hardware features, a brief introduction of the FIR filter the way to achieve the advantages and disadvantages of combining Altera s Stratix series of characteristics of the product, with a MAC based on the 8-order FIR digital filter design For example, given the use of Verilog hardware description language for digital logic design process and methods, and Quartus Ⅱ integrated development environment, prepared HDL code, for comprehensive utilization of Quartus Ⅱ emulator internal design so the impulse response simulation and verification.
Platform: | Size: 79872 | Author: sundan | Hits:

[VHDL-FPGA-Verilog] FIR

Description: FIR在FPGA中的VHDL代码实现教程-FIR in FPGA code in VHDL Tutorial
Platform: | Size: 20480 | Author: Mr Yang | Hits:

[VHDL-FPGA-Verilog] FIR_Direkt_BAB_P

Description: VHDL编写的代码。采用流水线方法实现的FIR滤波器。22阶。Fa=48kHz, Fc=10KHz。可用ModeSim仿真并FPGA实现-Code written in VHDL. Line method using the FIR filter. 22 bands. Fa = 48kHz, Fc = 10KHz. Can be used to achieve ModeSim simulation and FPGA
Platform: | Size: 1024 | Author: 李乔 | Hits:

[source in ebook] Finiteimpulseresponsefirfilter

Description: This code is a VHDL based code for FIR filter.A finite impulse response (FIR ) filter is a type of a digital filter. The impulse response, the filter s response to a Kronecker delta input, is finite because it settles to zero in a finite number of sample intervals.
Platform: | Size: 44032 | Author: kumar | Hits:

[VHDL-FPGA-Verilog] fir

Description: 数字电路设计中的，fir滤波器设计，我做的是8位宽的，利用vhdl实现，附带了完整的代码，报告，我没有对我的信息进行删除，是希望大家能够诚实的利用这个代码，提高自身本领。-Digital circuit design, fir filter design, I am doing is 8 bits wide, using vhdl implementation, with a complete code, the report, I did not delete my information in the hope that we can use this code for an honest to improve their skills.
Platform: | Size: 3322880 | Author: de de | Hits:

[VHDL-FPGA-Verilog] lowpowerfir

Description: This project was undertaken to produce a low power FIR filter for inclusion in a VHDL target library. The design was completed using OrCAD s Capture CIS, from this the VHDL code has been extracted. This method has allowed complete testing of the system. The power consumption of various arithmetic architectures has been investigated, and the results have been provided in the intial report (FIRLowPowerConsiderations.doc). These results have enabled the correct power/performance optimization for the FIR filter design.
Platform: | Size: 447488 | Author: Nagendran | Hits:

[VHDL-FPGA-Verilog] CSDmultiplier

Description: Code for CSD Multiplier
Platform: | Size: 1024 | Author: yuvi | Hits:

[VHDL-FPGA-Verilog] fir4tap1

Description: fir 4 tap code in VHDL
Platform: | Size: 2048 | Author: xyz002 | Hits:

[VHDL-FPGA-Verilog] FIR_1

Description: FIR code in vhdl -FIR code in vhdl ----VVV
Platform: | Size: 75776 | Author: hr | Hits:

[VHDL-FPGA-Verilog] FIR-LOOP-

Description: 数字接收机中的FIR滤波器，环形滤波器设计参考,VHDL代码-the FIR filter， loop filter design in a digital receiver,vhdl code
Platform: | Size: 1024 | Author: rickdecent | Hits:

[VHDL-FPGA-Verilog] FIR

Description: This FIR code wriiten in VHDL. This is 16 bit FIR tested on Spartan 3E kit-This is FIR code wriiten in VHDL. This is 16 bit FIR tested on Spartan 3E kit
Platform: | Size: 2669568 | Author: gurhans | Hits:

[OS program] FIR

Description: an FIR code which is writen in vhdl. this entity has clk and reseet inputs, and the filter output is provided as well. the coefficients of the filter are passed using a set of constants.
Platform: | Size: 3072 | Author: mohandes | Hits:

[VHDL-FPGA-Verilog] filtra-lowpass

Description: this a lowpass filtre in VHDL code with a test_bench you will find some specifications of the FIR-this is a lowpass filtre in VHDL code with a test_bench you will find some specifications of the FIR
Platform: | Size: 5120 | Author: mortadha | Hits:

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