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[VHDL-FPGA-Verilog] FIR低通滤波器部分模块

Description: 一个FIR低通滤波器,最小阻带衰减-30db,带内波动小于1db．用MAXPLUS2设计与仿真。-This is a FIR LPF, with-30dB in stop-band and sigma is less than 1dB. It is designed and simulated on MAXPLUS2.
Platform: | Size: 5120 | Author: 吴健宇 | Hits:

[VHDL-FPGA-Verilog] interpolation_FIR

Description: Interpolation FIR Design Example for Stratix Devices
Platform: | Size: 24576 | Author: Jack | Hits:

[VHDL-FPGA-Verilog] fir

Description: Verilog 程序， 实现4阶 fir-filter滤波器。 -Verilog procedures, to achieve 4-order filter fir-filter.
Platform: | Size: 1024 | Author: 左麟 | Hits:

[VHDL-FPGA-Verilog] 4

Description: 基于FPGA的FIR数字滤波器的设计与实现,基于FPGA的FIR数字滤波器的设计与实现-FPGA-based FIR digital filter design and implementation of FPGA-Based FIR Digital Filter Design and Implementation
Platform: | Size: 2337792 | Author: 南才北往 | Hits:

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