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[AI-NN-PR] IIRFIR

Description: 基于matlab和DSP的IIR/FIR 滤波器-Matlab and DSP-based IIR/FIR filter
Platform: | Size: 43008 | Author: 张晓光 | Hits:

[VHDL-FPGA-Verilog] iir

Description: 数字信号处理的fpga实现，用VHDL语言编程实现IIR滤波器-Digital signal processing to achieve the FPGA, using VHDL language programming to achieve IIR filter
Platform: | Size: 1024 | Author: songjunmin | Hits:

[VHDL-FPGA-Verilog] niosII_cyclone_1c20

Description: IIR、F FT各模块程序设计例程，可做为IP使用，初学者很有用-IIR, FIR, FFT modular design of the routines can be used as IP use, useful for beginners
Platform: | Size: 70656 | Author: 石林 | Hits:

[Other] IIR

Description: 毕业设计：基于FPGA的IIR滤波器设计-The design for IIR digital filter based on FPGA
Platform: | Size: 472064 | Author: lzndcb | Hits:

[Linux-Unix] Linux_bc

Description: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[Embeded-SCM Develop] 5

Description: 各种IIR及FIR数字滤波器的FPGA算法实验指导，适合新手学习。-A variety of IIR and FIR digital filter FPGA-algorithm experimental guide, suitable for novice to learn.
Platform: | Size: 1327104 | Author: 张狂 | Hits:

[VHDL-FPGA-Verilog] fir-and-iir

Description: FPGA关于数字滤波器设计,FIR的FPGA实现及其Quartus与MATLAB仿真-FPGA on the digital filter design, FIR s Quartus FPGA Implementation and Simulation with MATLAB
Platform: | Size: 5149696 | Author: 方明 | Hits:

[VHDL-FPGA-Verilog] Digital-Signal-Processing-with-FPGA

Description: FPGA结合DSP设计，如FIR、IIR滤波器，CORDIC算法,多重采样率信号处理，FFT,有对应的VHDL/Verilog 代码code-FPGA Combines with DSP, FIR 、IIR Digital Filters,CORDIC,FFT,Adaptive Filters，VHDL/Verilog code
Platform: | Size: 10501120 | Author: rickdecent | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 基于FPGA的IIR滤波器的各模块VHDL程序- such as in science and project technique. Compared with FIR digital filter, IIR digital filter can get high selectivity with low factorial.
Platform: | Size: 1024 | Author: 许成 | Hits:

[VHDL-FPGA-Verilog] graduate

Description: 基于fpga的IIR和FIR滤波器实现，里面有DA和AD模块，已经下载到板子上验证。-IIR and FIR filter fpga-based implementation, which has DA and AD modules have been downloaded to authenticate to the board.
Platform: | Size: 3428352 | Author: 黄建华 | Hits:

[Software Engineering] FPGA4JIIR

Description: 常用的数字滤波器有FIR数字滤波器和IIR数字滤波器｡ FIR数字滤波器具有精确的线性相位特性,在信号处理方面应用极为广泛,而且可以采用事先设计调试好的FIR数字滤波器IPCore来完成设计,例如Altera公司提供的针对Altera系列可编程器件的MegaCore,但是需要向Altera公司购买或申请试用版｡ 另外,对于相同的设计指标,FIR滤波器所要求的阶数比IIR滤波器高5~10倍,成本较高,而且信号的延迟也较大｡ IIR滤波器所要求的阶数不仅比FIR滤波器低,而且可以利用模拟滤波器的设计成果,设计工作量相对较小,采用FPGA实现的IIR滤波器同样具有多种优越性｡ -Commonly used digital filters have FIR digital filters and digital filter .FIR IIR digital filter has a precise linear phase characteristics, the signal processing is extensively used, and can be debugged using pre-designed FIR digital filter IPCore accomplished design, such as provided by Altera MegaCore Altera series for programmable devices, but need to purchase or apply for Altera trial version. in addition, for the same design specifications required by the order of the FIR filter IIR filters than high 5 ~ 10 times, high cost, and the order of the delayed signal is also larger .IIR filter required not only lower than the FIR filter, and can use the results of the analog filter design, design work is relatively small, using FPGA IIR filters also have a variety of advantages.
Platform: | Size: 154624 | Author: super | Hits:

[source in ebook] Digital-signal-process-of-PFGA

Description: 数字信号处理 包括滤波器IIR FIR CORDIC的FPGA实现 资料中是VHDL语言 相应的配套包verilog程序-Digital signal processing includes a filter IIR FIR CORDIC on FPGA is VHDL language data corresponding supporting package verilog program
Platform: | Size: 10710016 | Author: liyinghui | Hits:

[VHDL-FPGA-Verilog] FPGA_fir

Description: FPGA/CPLD设计数字滤波器（FIR和IIR），已经仿真测试-FPGA/CPLD design digital filters (FIR and IIR), has simulation test
Platform: | Size: 139264 | Author: bill | Hits:

[Software Engineering] DSP-with-FPGAs

Description: Field-programmable gate arrays (FPGAs) are on the verge of revolutionizing digital signal processing in the manner that programmable digital signal processors (PDSPs) did nearly two decades ago. Many front-end digital signal processing (DSP) algorithms, such as FFTs, FIR or IIR filters, to name just a few, previously built with ASICs or PDSPs, are now most often replaced by FPGAs. Modern FPGA families provide DSP arithmetic support with fast-carry chains (Xilinx Virtex, Altera FLEX) that are used to implement multiply-accumulates (MACs) at high speed, with low overhead and low costs [1]. Previous FPGA families have most often targeted TTL “glue logic” and did not have the high gate count needed for DSP functions. The efficient implementation of these front-end algorithms is the main goal of this book.
Platform: | Size: 8656896 | Author: Alexander | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 《数字信号处理的FPGA实现（第三版）》作者：U.Meyer-Baese 的配套源码，基于quartus9.0编写，使用的cyclone ii。其中包含FIR IIR FFT等算法的实现，对学习图像处理很有帮助。- FPGA digital signal processing (third edition) Author: U.Meyer-Baese The matching source, based on quartus9.0 preparation, the use of cyclone ii. Which includes FIR IIR FFT algorithm such as the realization of learning to image processing helpful.
Platform: | Size: 417792 | Author: 马博城 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 《数字信号处理的FPGA实现（第三版）》作者：U.Meyer-Baese 的配套源码，基于quartus9.0用VHDL编写，使用的cyclone ii。其中包含FIR IIR FFT等算法的实现，对学习图像处理很有帮助。- FPGA digital signal processing (third edition) Author: U.Meyer-Baese The matching source, based on quartus9.0 prepared using VHDL, the use of cyclone ii. Which includes FIR IIR FFT algorithm such as the realization of learning to image processing helpful.
Platform: | Size: 397312 | Author: 马博城 | Hits:

[VHDL-FPGA-Verilog] DIGITAL-SIGNAL-PROCESSING-WITH-FPGA

Description: 数字信号处理的FPGA实现最新版的源代码，涉及FFT变换、IIR、FIR数字滤波器等的verilog及vhdl代码-<digital signal processing with FPGA> (the latest version) . the source code involving FFT transform, IIR, FIR digital filters by verilog and vhdl.
Platform: | Size: 19156992 | Author: Rick007007 | Hits:

[Other] yqgti

Description: Single path or multipath Rayleigh fading channel simulation, Robustness, superior performance, Bottom-pass and band-pass FIR and IIR filter bottom pass and band-pass filter.
Platform: | Size: 8192 | Author: grefcmud | Hits:

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