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[VHDL-FPGA-Verilog] simple_fm_receiver.tar

Description: FM收音机的解码及控制器VHDL语言实现，Xilinx提供的．别谢我．-FM radio decoder and controller VHDL, Xilinx provide. I thank other.
Platform: | Size: 70656 | Author: 喻袁洲 | Hits:

[VHDL-FPGA-Verilog] all_digital_fm_receiver.tar

Description: 全数字fM接受机包括，测试代码，说明文档，还有源代码-All-digital FM receivers, including, test code, documentation, and source code
Platform: | Size: 669696 | Author: 聂样 | Hits:

[VHDL-FPGA-Verilog] kuoping

Description: fpga嵌入式设计 扩频接收机设计 有matlab 和vhdl 对比情况-Design of spread-spectrum receiver embedded FPGA design and VHDL contrast matlab
Platform: | Size: 363520 | Author: 龙丽丽 | Hits:

[Audio program] simple_fm_receiver.tar

Description: 一个简单FM接收机的VHDL源码，很有参考意义-A simple FM receiver VHDL source code is very useful
Platform: | Size: 632832 | Author: metallica | Hits:

[VHDL-FPGA-Verilog] fm

Description: VHDL设计全数字FM接收机 资料大小：650KB 运行环境：Windows -VHDL design of all-digital FM receiver Data Size: 650KB operating environment: Windows
Platform: | Size: 665600 | Author: 古月 | Hits:

[Communication-Mobile] FMreceiver

Description: FM receiver VHDL code
Platform: | Size: 775168 | Author: nan | Hits:

[Modem program] all_digital_fm_receiver_latest

Description: Fm receiver using DP-Fm receiver using DPLL
Platform: | Size: 112640 | Author: sai | Hits:

[VHDL-FPGA-Verilog] all-digital-fm-receiver

Description: all digital fm receiver using vhdl programming language project for electronics and communication engineering students.
Platform: | Size: 1545216 | Author: Rahul | Hits:

[SCM] adfmreceiver

Description: The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency,iωand the respective output frequency,oωvia phase comparison. This self-correcting ability of the system also allows the PLL to track the frequency changes of the input signal once it is locked. Frequency modulated input signal is assumed as a series of numerical values (digital signal) via 8-bit of analog to digital conversion (ADC) circuit. The FM Receiver gets the 8 bit signal every clock cycle and outputs the demodulated signal. The All Digital FM Receiver circuit is designed using VHDL, then simulated and synthesized using ModelSim SE 6 simulator and Xilinx ISE 6.3i, respectively. FPGA implementation also provided, here we use Virtex2 device.
Platform: | Size: 658432 | Author: vijay | Hits:

[VHDL-FPGA-Verilog] simple_fm_receiver_latest.tar

Description: 用FPGA实现简单的FM接收机，d/a模块用扬声器-FPGA implementation using a simple FM receiver, d/a module with speaker
Platform: | Size: 1581056 | Author: 张昆 | Hits:

[VHDL-FPGA-Verilog] DigitalFM

Description: 用VHDL编写的一个全数字FM调谐接收机的源代码和详细资料，原文是英文，已经翻译成中文。 -One using VHDL digital FM tuner receiver source code and detailed information, the original is in English, has been translated into Chinese.
Platform: | Size: 1453056 | Author: xuegamgma | Hits:

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