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Description: para13：
fifo.vhd FIFO（双口RAM）
fifo1.vhd FIFO（嵌入式EAB）
fifo2.vhd FIFO（LPM）-para13: fifo.vhd FIFO (dual port RAM) fifo1.vhd FIFO (embedded EAB) fifo2.vhd FIFO (LPM)
Platform: |
Size: 3072 |
Author: libing |
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Description: 正弦信号发生器的设计,正弦信号发生器的结构由3 部分组成。数据计数器或地址发生器、数据ROM 和D/A。性能良好的正弦信号发生器的设计要求此3 部分具有高速性能，且数据ROM 在高速条件下，占用最少的逻辑资源，设计流程最便捷，波形数据获最方便。下图是此信号发生器结构图，顶层文件SINGT.VHD 在FPGA 中实现，包含2 个部分：ROM 的地址信号发生器，由5 位计数器担任，和正弦数据ROM，拒此，ROM由LPM_ROM模块构成能达到最优设计，LPM_ROM底层是FPGA中的EAB或ESB等。地址发生器的时钟CLK的输入频率f0与每周期的波形数据点数（在此选择64 点），以及D/A输出的频率f 的关系是：f=f0/64。-Sinusoidal signal generator design, the structure of the sinusoidal signal generator consists of three parts. The data counter, or address generator, data ROM and D/A. The good performance of the sinusoidal signal generator design requirements Part 3 high-speed performance, and the ROM data in high-speed conditions, take up minimal logic resources, the design process is the most convenient, the waveform data is the most convenient. The following figure is a block diagram of this signal generator, top file SINGT.VHD is implemented in FPGA, consists of two parts: ROM address signal generator, served by the 5-bit counter, and the sine ROM reject this ROM by LPM_ROM module constitute optimal design LPM_ROM is the underlying FPGA EAB or ESB. The address generator clock CLK input frequency f0 and per period of the waveform data points selected in (64), and the relationship between D/A output frequency f is: f = f0/64.
Platform: |
Size: 1825792 |
Author: 吴祥 |
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