Search - FPGA F

[VHDL-FPGA-Verilog] ModelSim6c_SE_Cracker

Description: crack for ModelSim, a Verilog, VHDL and mixed VHDL / Verilog CAD simulator for FPGA, board and IC design.-crack for ModelSim, a Verilog. VHDL and mixed VHDL/Verilog simulator for CAD F PGA, board and IC design.
Platform: | Size: 292864 | Author: 陈亨利 | Hits:

[VHDL-FPGA-Verilog] ps2_vhdl

Description: 利用vhdl实现FPGA芯片从PS2键盘读出数据(0-F) 并在数码管上显示 -use FPGA chip from the PS2 keyboard sensed data (0-F) and displayed on a digital control
Platform: | Size: 1024 | Author: 刘音 | Hits:

[Software Engineering] firfilterdesignoffpga

Description: 提出了一种基于FPGA的高阶高速F IR滤波器的设计与实现方法。通过一个169阶的均方根升余弦滚降滤波器的设计,介绍了如何应用流水线技术来设计高阶高速F IR滤波器,并且对所设计的 FIR滤波器性能、资源占用进行了分析。-A high-level FPGA-based high-speed F IR filter design and implementation. Through a 169-order root mean square raised cosine filter roll-off design, describes how the application of technology to design high-end line of high-speed F IR filter, and for the design of FIR filter performance, resources to carry out an analysis of the occupier.
Platform: | Size: 208896 | Author: 王晓岚 | Hits:

[Other] 01

Description: FPGA实现FFT算法 F PGA实现FFT算法-FPGA realize F PGA realize FFT algorithm FFT algorithm
Platform: | Size: 783360 | Author: zhou wan | Hits:

[VHDL-FPGA-Verilog] xc3s400

Description: xc3s400芯片详细的英文资料，xc3s400的FPGA开发板使用者必看-chip xc3s400 detailed information in English, xc3s400 the FPGA development board users see
Platform: | Size: 1542144 | Author: 黄天乐 | Hits:

[Software Engineering] a+f

Description: 采用ARM和FPGA组合，共同实现电脑横机控制器-The use of ARM and FPGA combination of a common computerized flat knitting machine controller
Platform: | Size: 124928 | Author: wangmixia | Hits:

[VHDL-FPGA-Verilog] FFT_VHDL

Description: FFT的FPGA实现里面有测试程序。希望对FPGA的学习朋友有所帮助！-FFT of the FPGA test procedure to achieve there. FPGA want to be helpful to learn a friend!
Platform: | Size: 437248 | Author: 夏浪 | Hits:

[VHDL-FPGA-Verilog] Mars-SP3-U_FPGA_manual

Description: Mars-SP3-U FPGA开发板说明，针对Xilinx的XC3S400，有对原理图的说明和实例操作说明-Mars-SP3-U FPGA development board that Xilinx for the XC3S400, there is schematic diagram of the description and examples of instructions
Platform: | Size: 645120 | Author: iversn | Hits:

[VHDL-FPGA-Verilog] niosII_cyclone_1c20

Description: IIR、F FT各模块程序设计例程，可做为IP使用，初学者很有用-IIR, FIR, FFT modular design of the routines can be used as IP use, useful for beginners
Platform: | Size: 70656 | Author: 石林 | Hits:

[Books] dds

Description: FPGA实现DDS，f=90kHZ~5MHZ范围-FPGA realization of DDS, f = 90kHZ ~ 5MHZ the scope of
Platform: | Size: 1442816 | Author: 王勤 | Hits:

[VHDL-FPGA-Verilog] FPQ

Description: 基于FPGA的数控分频器，可以吧一个时钟信号分成不同频率的时钟信号。-FPGA-based digital frequency divider, a clock signal can now be divided into different frequency clock signals.
Platform: | Size: 3072 | Author: 静 | Hits:

[VHDL-FPGA-Verilog] 4

Description: 基于FPGA的FIR数字滤波器的设计与实现,基于FPGA的FIR数字滤波器的设计与实现-FPGA-based FIR digital filter design and implementation of FPGA-Based FIR Digital Filter Design and Implementation
Platform: | Size: 2337792 | Author: 南才北往 | Hits:

[VHDL-FPGA-Verilog] reload_fir

Description: 这是我在Xilinx公司的FPGA上实现的FIR滤波器，调用的内部核，其特色是可以用较少的资源实现该功能，而且可以实现参数重载，即从外部MCU设置FIR滤波器的参数-This is my Xilinx FPGA to achieve the FIR filter, called internal audit, its characteristics can be achieved with fewer resources to this function, and the overload parameters can be achieved, that is, from an external MCU to set the parameters of FIR Filter
Platform: | Size: 16727040 | Author: 林寒风 | Hits:

[Other] 68013

Description: 介绍了此控制器与FPGA接口的控制和HDL (硬件描述语言)实现方法。利用CY7C68013控制器的 Slave F IFO从机方式,用Verilog HDL在FPGA中产生相应的控制信号,实现对数据的快速读写。试验结果表明此方案传输速度快、数据准确,可扩展到其他需要通过USB进行快速数据传输的系统中-This paper describes the controller and the FPGA interface to control and HDL (hardware description language) implementations. Use CY7C68013 controller Slave F IFO slave mode, using Verilog HDL in the FPGA generate a corresponding control signal to achieve fast read and write data. The results show that this program transmission speed, accurate data can be expanded to other needs through the USB for fast data transfer system
Platform: | Size: 365568 | Author: 余岳衡 | Hits:

[VHDL-FPGA-Verilog] altera_fft

Description: alter官方fft程序使用verilog编写需要的同学可以下载-alter the official fft program uses verilog prepared students in need can be downloaded
Platform: | Size: 989184 | Author: 廖国杰 | Hits:

[VHDL-FPGA-Verilog] WCDMA-Frequency-Domain-Interference-Cancellation-f

Description: WCDMA数字频域干扰抵消器，绝对的高手写的文档和代码，里面资料齐全方便自学，是很好的学习FPGA实现无线通信模块的资料。-WCDMA Frequency Domain Interference Cancellation figures, the absolute master of written documentation and code, which complete information to facilitate self-learning, is a very good learning FPGA implementation of wireless communications and information.
Platform: | Size: 2325504 | Author: lrj | Hits:

[VHDL-FPGA-Verilog] f

Description: 为了解决传统的维特比译码器结构复杂、译码速度慢、消耗资源大的问题，提出一种新型的适用于FPGA特点，路径存储与译码输出并行工作，同步存储路径矢量和状态矢量的译码器设计方案。该设计方案通过仿真验证，译码结果正确，得到编码前的原始码元，速度显著提高，译码器复杂程度明显降低,性能优良。-The convolution code
Platform: | Size: 12288 | Author: wang zhi | Hits:

[VHDL-FPGA-Verilog] FPGA-DISPLAY-0_F

Description: FPGA 开发板试验例程，在数码管实现0-F的显示-FPGA development board test routines in the digital display tube 0-F
Platform: | Size: 283648 | Author: wills | Hits:

[Embeded-SCM Develop] dr6—ise-F

Description: 用FPGA开发板的按键作为电子表的时间初值设置控制信号，数码管当前时间值输出。用按键选择分别输出：分、秒、1/10秒。(With FPGA development board button, as the time value of the electronic table, set the control signal, digital tube current time value output. Select output by buttons: minutes, seconds, and 1/10 seconds.)
Platform: | Size: 338944 | Author: dr0325 | Hits:

[Other] 用FPGA实现ATM信元的字头处理_邹扬真

Description: 本文探讨了采用F P G A X 3 0 0 o 系列芯片实现独立于承载码流结构的A T M 信元字头处理器的可能性. 针对F P G A 处理速度相对低于可能的承载码流速率的问题. 着重研究了字头H E C 字段生成、扰码、信元定界、解扰等过程的并行处理算法
Platform: | Size: 422681 | Author: shandongtou | Hits:

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