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Description: 说明:这个代码是基于FPGA的数字IIR无限长冲激响应滤波器的源代码.-Note : This code is based on the number of FPGA IIR infinite impulse response filter the source code.
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Size: 1084 |
Author: 李军 |
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Description: Xilinx FPGA设计进阶(提高篇)-advanced Xilinx FPGA design (Advancement Part 1)
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Size: 2460672 |
Author: 郑忡 |
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Description: 这是DSP实现的无线冲击(IIR)滤波器的实现,用c语言编写,一调试通过-This is the wireless DSP shocks (IIR) filter achieved with c language, through a debugger
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Size: 52224 |
Author: 朱敬锋 |
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Description: 说明:这个代码是基于FPGA的数字IIR无限长冲激响应滤波器的源代码.-Note : This code is based on the number of FPGA IIR infinite impulse response filter the source code.
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Size: 1024 |
Author: 李军 |
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Description: IIR-butter低通滤波器设计,数字信号处理专业学生的课程设计。-IIR-butter low-pass filter design, digital signal processing professional students in curriculum design.
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Size: 30720 |
Author: qjyong |
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Description: (1)设计一个直接型二阶低通数字滤波器。
(2)在DSP TMS320C5402上实现IIR滤波。
(3)对IIR滤波器各项指标进行评价
-(1) design a second direct-digital low-pass filter. (2) on the TMS320C5402 DSP IIR filter. (3) right IIR filter evaluation indicators
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Size: 3072 |
Author: 深蓝 |
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Description: 数字信号处理的fpga实现,用VHDL语言编程实现IIR滤波器-Digital signal processing to achieve the FPGA, using VHDL language programming to achieve IIR filter
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Size: 1024 |
Author: songjunmin |
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Description: 介绍了IIR 滤波器的FPGA 实现方法,给出了 IIR 数字滤波器的时序控制、延时、补码乘法和累加四个模块的设计方法,并用VHDL和FPGA 器件实现了IIR 数字滤波。-Introduction of the IIR filter FPGA implementation method of IIR digital filter timing control, delay, multiplication and accumulation complement the four modules of the design method and device using VHDL and FPGA implementation of IIR digital filter.
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Size: 661504 |
Author: 杨培科 |
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Description: 毕业设计:基于FPGA的IIR滤波器设计-The design for IIR digital filter based on FPGA
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Size: 472064 |
Author: lzndcb |
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Description: 对vga接口做了详细的介绍,并且有一
·三段式Verilog的IDE程序,但只有DMA
·电子密码锁,基于fpga实现,密码正
·IIR、FIR、FFT各模块程序设计例程,
·基于逻辑工具的以太网开发,基于逻
·自己写的一个测温元件(ds18b20)的
·光纤通信中的SDH数据帧解析及提取的
·VHDL Programming by Example(McGr
·这是CAN总线控制器的IP核,源码是由
·FPGA设计的SDRAM控制器,有仿真代码
·xilinx fpga 下的IDE控制器原代码,
·用verilog写的,基于查表法实现的LO
·精通verilog HDL语言编- up:in STD_LOGIC
down:in STD_LOGIC
run_stop:in STD_LOGIC
wai_t: in std_logic_vector(2 downto 0)
lift:in std_logic_vector(2 downto 0)
ladd: out std_logic_vector(1 downto 0)
)
end control
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Size: 18683904 |
Author: liuzhou |
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Description: FPGA的IIR算法描述,希望对大家有用-IRR arithetics using fpga
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Size: 1024 |
Author: Denny |
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Description: IIR50HZ的数字陷波器的FPGA实现-IIR50HZ digital notch filter implementation in FPGA
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Size: 471040 |
Author: kudding |
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Description: 用MATLAB设计及FPGA实现IIR滤波器的方法
摘要 本文介绍了IIR数字滤波器的传统设计思想与步骤及计算机辅助设计方法。并在FPGA上高效实现的低阶IIR滤波
器,其阶数低,实时响应快,适合雷达等的实时、高效处理环境。利用IIR滤波器的多相结构来实现该滤波器系统的方法,对于
四通道的情形在MATLAB上利用Simulink作了仿真, 并在目标板上对算法进行了实现,证明该系统能够同时处理四个通道的信号。-Using MATLAB Design and FPGA realization IIR Filter method Abstract This paper introduces IIR digital filter traditional design Thought and steps and CAD method. And FPGA on efficient realization low IIR filter, its order low, real response fast suitable radar real time, efficient processing environment. Use IIR filter multiphase structure realize the filter systematic method, for four channel circumstances in MATLAB on use Simulink made simulation and target board algorithm was realized proved system can simultaneously four channel signal.
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Size: 2021376 |
Author: sfef |
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Description: 基于fpga的数字滤波器设计的vhdl源代码-Fpga digital filter design based on the vhdl source code
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Size: 7168 |
Author: sunnyhp |
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Description: iir滤波器的fpga实现,教你如何用vhdl描述一个iir滤波器-iir filter fpga implementation, teach you how to describe a iir filter vhdl
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Size: 4523008 |
Author: 王程序 |
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Description: FPGA关于数字滤波器设计,FIR的FPGA实现及其Quartus与MATLAB仿真-FPGA on the digital filter design, FIR s Quartus FPGA Implementation and Simulation with MATLAB
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Size: 5149696 |
Author: 方明 |
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Description: FPGA结合DSP设计,如FIR、IIR滤波器,CORDIC算法,多重采样率信号处理,FFT,有对应的VHDL/Verilog 代码code-FPGA Combines with DSP, FIR 、IIR Digital Filters,CORDIC,FFT,Adaptive Filters,VHDL/Verilog code
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Size: 10501120 |
Author: rickdecent |
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Description: 基于FPGA的IIR低通数字滤波器设计
IIR low-pass digital filter design based on FPGA-IIR low-pass digital filter design based on FPGA
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Size: 2048 |
Author: wy |
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Description: 积分器的一种实现方法:每级积分器都是一个反馈系数为1的单极点IIR滤波器, 其传递函数为:(An implementation of an integrator: each stage integrator is a single pole IIR filter with a feedback factor of 1:)
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Size: 139264 |
Author: 所罗门
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Description: 基于verilog hdl语言对IIR滤波器设计(Design of IIR filter based on Verilog HDL language)
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Size: 1688576 |
Author: jmcjgp
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