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[VHDL-FPGA-VerilogSPWM

Description: VHDL采用自然采样法写的SPWM,里面有正弦表,可以通过外接输入正弦波和三角波的频率。 -VHDL using written natural sampling SPWM, there are sine table, you can enter through the external sinusoidal and triangular wave frequency.
Platform: | Size: 7168 | Author: zyb | Hits:

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