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[Other resource] CU.v

Description: 用vlog语言编写的cpu控制器源代码，用于fpga的硬件编程实验-vlog language used in the preparation of cpu controller source code for programming fpga hardware experiments
Platform: | Size: 1108 | Author: ansiwei | Hits:

[VHDL-FPGA-Verilog] Verilog&Vhdl混语言对SDRAM的控制源代码

Description: Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
Platform: | Size: 249856 | Author: 飞扬 | Hits:

[VHDL-FPGA-Verilog] PLI

Description:
Platform: | Size: 4096 | Author: 陈正一 | Hits:

[VHDL-FPGA-Verilog] Arbiter

Description: Arbiter.v verilog实现 三路请求，使用循环策略的仲裁器 含有看门狗电路-Arbiter.v Verilog achieve three road request, the use of recycled strategy for containing the arbitration watchdog circuit
Platform: | Size: 2048 | Author: 夏虫 | Hits:

[VHDL-FPGA-Verilog] qdesigns

Description: 关于Altera公司FPGA编程的一些常用实例代码.-on Altera FPGA programming examples of some commonly used code.
Platform: | Size: 89088 | Author: Newton81 | Hits:

[Button control] 4yue11haoxiawu

Description: 1、基于FPGA实现FIR数字滤波器的研究（使用VHDL语言进行编程） 2、多功能单片机下载开发软硬件的设计（利用VB或V C++和C语言）有下载板和下载软件 3、迷你播放器（利用Visual Basic 6.0设计）可以播放多种格式的音乐和电影，以及图片浏览等等 4、小电容小电感测试仪 -1, FPGA-based digital FIR filter (use VHDL program) 2. Multi-function download the software and hardware design development (VB or V C and C language), downloading software and download Plate 3, Player (using Visual Basic 6.0 design) can play multiple formats of music and movies, Photo View and so on four small small inductance capacitor tester
Platform: | Size: 16384 | Author: wangxing | Hits:

[SCM] AD_ASM_AD0832shuzidianyabiaoLED

Description: 数字电压表 AD芯片： 采用8位串行A/D转换器ADC0832。 ● 8位分辨率，逐次逼近型，基准电压为 5V ● 5V单电源供电 ● 输入模拟信号电压范围为 0～5V ● 有两个可供选择的模拟输入通道 显示： 使用三个数码管。 显示范围： 0.00 － 5.10 （单位：V） 连接方式： AD_CLK → P1.0 AD_DAT → P1.1 AD_CS → P3.4 模拟输入 → CH0 (AD_DAT = DO + DI) ADC0832输出最大转换值＝FFH (255) 设定最大测量值＝5.1V 255X=5.1 X=0.02 即先乘2再除以100 （小数点放在第三位数码管）- Digital voltmeter AD chip: Uses 8 serial A/D switch ADC0832.* 8 resolution, gradually approaching, the datum voltage is 5V* the 5V single power source power supply* input simulated signal voltage scope is 0 ~ 5V* has two to be possible to supply the choice the analog input channel Demonstrated: Uses three digital tubes. Demonstrates the scope: 0.00- 5.10 (unit: V) Connection way: AD_CLK-> P1.0 AD_DAT-> P1.1 AD_CS-> P3.4 analog input-> CH0 (AD_DAT = DO DI) ADC0832 output biggest transformation value = FFH (255) establishes greatest observed value = 5.1V 255X=5.1 X=0.02 namely first to ride 2 to eliminate again by 100 (decimal point puts on third digital tube)
Platform: | Size: 7168 | Author: lmhit | Hits:

[Other] VHDL_and_FPGA_design

Description: 本书的)4一个持色是从FPGA设计的角度出发．别祈了vHD巳语法的特点以及它们的正 确使用方沈，将初学者在运用vHDL语吉进行FPrjA设计中会遇到的疑惑，— 点拨清楚。 并纪合作者的多年FPGA设计经验，讲述厂许多EDA设计思想v并贯穿全书始终。 -the book) with a four color from the FPGA design point of view. Other vHD already have a prayer of the characteristics of grammar and the correct use of them, Shen Fang, beginners in the use of the phrase Kyrgyzstan vHDL for FPrjA design encounter puzzled-Inspiration clear. SUMMARY collaborators and FPGA design experience for many years, on many plants v EDA design ideas and has always run through the whole book.
Platform: | Size: 7979008 | Author: haopowan | Hits:

[source in ebook] mt48lc4m32b2

Description: mt48lc4m32b2.v 是128M sdram 中典型设计。。可以借鉴。-mt48lc4m32b2.v 128M sdram is typical design. . Be used.
Platform: | Size: 8192 | Author: chenliang | Hits:

[Special Effects] tv_vga

Description: 将TV信号转换到VGA信号，通过FPGA的转换可以直接在显示器上显示。-TV signals will switch to VGA signal, through the FPGA conversion can be directly displayed on the monitor.
Platform: | Size: 2048 | Author: gm | Hits:

[VHDL-FPGA-Verilog] S6_VGA_change

Description: verilog源代码，quartusII工程。程序实现VGA时序。控制VGA显示器输出图形。在quartusII中客直接运行，-Verilog source code, quartusII works. Procedures to achieve VGA timing. VGA graphics display control output. QuartusII in the direct run-off,
Platform: | Size: 2572288 | Author: 李晨 | Hits:

[Special Effects] video_timing_gen1

Description: 各种制式的视频信号输出时序产生的源代码。可以直接用FPGA综合得到电路-A variety of standard video signal output timing generated by the source code. Can be directly used for FPGA integrated circuits
Platform: | Size: 5120 | Author: scounix | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA设计全流程：Modelsim>>Synplify.Pro>>ISE 第一章 Modelsim编译Xilinx库 第二章 调用Xilinx CORE-Generator 第三章 使用Synplify.Pro综合HDL和内核 第四章 综合后的项目执行 第五章 不同类型结构的仿真-FPGA design of the whole process: Modelsim>> Synplify.Pro>> ISE Chapter ModelSim Xilinx compiler library chapter called Xilinx CORE-Generator Chapter III Synplify.Pro integrated use of Chapter IV of HDL and kernel integrated implementation of the project after the Chapter V structure of different types of simulation
Platform: | Size: 218112 | Author: 青岚之风 | Hits:

[VHDL-FPGA-Verilog] fpga

Description: 无线光通信技术具有通信容量大、传输速率高等众多优点, 在许多场合都有重要的应用, 是现代通信技术研究的一个热点。由于脉冲位置调制 ( PPM ) 有较高的平均功率利用率和抗干扰能力, 故 PPM是无线光通信系统中常用的调制方式。在研究 PPM调制技术的基础上, 就基于 FPG A的无线光通信 PPM调制系统进行设计, 并用 V H D L语言完成了系统的设计和仿真。仿真结果表明, 该设计具有正确性和合理性。-Wireless optical communication technology has the communications capacity, many of the benefits of higher transmission rates, in many occasions have important applications in modern communication technologies are a hot research. Because of pulse position modulation (PPM) have a higher average power utilization and anti-interference ability, so PPM is a wireless optical communication system commonly used in modulation. PPM modulation technique in the study on the basis of FPG A based on wireless optical communication PPM modulation system design, and VHDL language achieve the system design and simulation. Simulation results show that the rationality of the design right.
Platform: | Size: 194560 | Author: 朱雯 | Hits:

[VHDL-FPGA-Verilog] VGA(FPGA)

Description: 基于FPGA的VGA工程文件以及相应的参考资料-FPGA-based VGA engineering documents and the corresponding reference
Platform: | Size: 4240384 | Author: 高天天 | Hits:

[VHDL-FPGA-Verilog] fifo_test.v.tar

Description: code for implementing high speed fifo for apturing data from fpga-code for for implementing high speed fifo for apturing data from fpga
Platform: | Size: 2048 | Author: Vikas | Hits:

[VHDL-FPGA-Verilog] RAW2RGB.v

Description: RGB-raw2RGB converting data from Cmos camera to FPGA
Platform: | Size: 2048 | Author: imag3ne | Hits:

[VHDL-FPGA-Verilog] MEDIAN.v

Description: fpga 的 median的verilog实现-median of verilog implementation
Platform: | Size: 1024 | Author: xyz | Hits:

[Embeded Linux] Cyclone V HPP demonstration

Description: C source code that exemplifies the use of the Cyclone V FPGA on a development board. Function exemplified: - the communication between the HPP and the FPGA - using the audio output - using LEDs - using switches - using 7 segment display
Platform: | Size: 12241 | Author: serby2000 | Hits:

[VHDL-FPGA-Verilog] FPGA黑金开发板AX301原理图

Description: 掌 握 V e r i l o g H D L 语 言 需 要 的 不 只 是 技 术 而已 ， 最 重 要 是 那 颗 安 静 的 心 ， 安 静 的 心 会 带 读 者 乘 风 破 浪 ， 一 方 通 行 。 此 外 记 录 笔 记 的习 惯 更 为 重 要 ， 向 自 己 学 习 比 起 向 他 人 学 习 更 有 学 习 的 价 值 。(It is not only the skill that is required to hold V e r I l o g H D l, but the most important thing is the quiet heart, the quiet heart will take the reader in the wind to break the waves, and the one side will pass.The habit of recording and recording is more important, and it is more valuable to learn from him than to learn from him.)
Platform: | Size: 117760 | Author: 你四哥 | Hits:
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