Search - FPGA cpu

[Documents] FPGA_ASIC-基于同步原则的FPGA-CPU设计.rar

Description: FPGA_ASIC-基于同步原则的FPGA-CPU设计.rar
Platform: | Size: 179660 | Author: changroc | Hits:

[DSP program] TMS320C54x DSP 的cpu和外围设备

Description: 针对在FPGA中实现FIR滤波器的关键--乘法运算的高效实现进行了研究，给了了将乘法化为查表的DA算法，并采用这一算法设计了FIR滤波器。通过FPGA仿零点验证，证明了这一方法是可行和高效的，其实现的滤波器的性能优于用DSP和传统方法实现FIR滤波器。最后介绍整数的CSD表示和还处于研究阶段的根据FPGA实现的要求改进的最优表示。-view of the FPGA FIR filters achieve the key-- the multiplication Efficient Implementation of research, to the multiplication of the DA into Lookup algorithm, and using the algorithm design of the FIR filter. FPGA through imitation 0.1 certification proves that the method is feasible and efficient, achieve superior filter performance DSP and traditional FIR filter method. Finally, integral and said the CSD is still in the research stage on the basis of FPGA requirements of the optimal said.
Platform: | Size: 1424384 | Author: 呈一 | Hits:

[Other] VHDL-FPGA-clock

Description: ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
Platform: | Size: 269312 | Author: 王越 | Hits:

[VHDL-FPGA-Verilog] cpu-leon3-altera-ep1c20

Description: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了在Altera公司的ep1c20 FPGA的位码文件和配置文件，可以直接下载使用！-A VHDL design with the use of powerful 32-bit CPU, this document contains Altera Corporation in the ep1c20 FPGA code and configuration files, you can direct download!
Platform: | Size: 687104 | Author: zhao onely | Hits:

[Internet-Network] FPGACPU

Description: FPGA RSIC CPU设计文档和源码是EDA中对CPU设计非常好用的程序-FPGA RSIC CPU design documents and source code is the EDA design for CPU-to-use procedures
Platform: | Size: 403456 | Author: zhl | Hits:

[VHDL-FPGA-Verilog] lab80

Description: 基于FPGA的CPU设计 VHDL 编写-FPGA-CPU design based on VHDL prepared
Platform: | Size: 3051520 | Author: 鹏鹏 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 使用verilog作为CPU设计语言实现单数据通路五级流水线的CPU。具有32个通用寄存器、一个程序计数器PC、一个标志寄存器FLAG，一个堆栈寄存器STACK。存储器寻址粒度为字节。数据存储以32位字对准。采用32位定长指令格式，采用Load/Store结构，ALU指令采用三地址格式。支持有符号和无符号整数加、减、乘、除运算，并支持浮点数加、减、乘、除四种运算，支持与、或、异或、非4种逻辑运算，支持逻辑左移、逻辑右移、算术右移、循环右移4种移位运算，支持Load/Store操作，支持地址/立即数加载操作，支持无条件转移和为0转移、非0转移、无符号>转移、无符号<转移、有符号>转移、有符号<转移等条件转移。
Platform: | Size: 43008 | Author: haotianr | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 关于FPGA的CPU的设计，可以看一下，大家讨论学习一下啊-The CPU on the FPGA design, you can see, we discussed learning about ah
Platform: | Size: 3072 | Author: 王飞 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the final design of the micro-operation microinstruction to verify the correctness of the design. Can achieve the basic add, subtract, multiply, divide, transfer, recycling and other operations.
Platform: | Size: 1268736 | Author: Rachel | Hits:

[VHDL-FPGA-Verilog] CPU-Altera-FPGA

Description: 用CPU配置Altera公司的FPGA，简单明了，通俗易懂。-EASY TO USE
Platform: | Size: 181248 | Author: zhangfan | Hits:

[VHDL-FPGA-Verilog] soc-gr0040-010309

Description: xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
Platform: | Size: 406528 | Author: urga turg | Hits:

[VHDL-FPGA-Verilog] lariviere2008uclinux

Description: xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
Platform: | Size: 252928 | Author: urga turg | Hits:

[Software Engineering] CPU_Architecture

Description: Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets. The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism. -Our processor is a RISC processor that can be used for many general applications, but it is specially designed for the purpose of high speed network related tasks. External hardware accelerator is used for network packet processing. The common network tasks include CRC and Checksum calculations that are used for validation of data integrity in the network packets. The accelerator unit is able to perform a checksum and CRC calculation autonomously without CPU interactions using a build in DMA mechanism.
Platform: | Size: 2506752 | Author: Amit Adoni | Hits:

[Software Engineering] FPGA-cpu

Description: 基于FPGA的简易处理器设计2010/05/04-A simple FPGA-based processor design 2010/05/04
Platform: | Size: 98304 | Author: 阿锦 | Hits:

[VHDL-FPGA-Verilog] Convolution_filter-fpga

Description: Implementation of a 2D Convolution Filter on FPGA. Performance evaluation between CPU, GBU and FPGA
Platform: | Size: 52224 | Author: Birrax | Hits:

[Other] FPGA-CPU-DIY

Description: 中文名：FPGA CPU设计和制作计算机利用可编程逻辑器件制作个人用的计算机-Chinese name: FPGA CPU design and production of computer production of personal computers using programmable logic devices
Platform: | Size: 218112 | Author: john | Hits:

[VHDL-FPGA-Verilog] base-on-FPGA-cpu-

Description: 基于FPGA的嵌入式CPU的制作，包含了代码和测试程序，以及在UBUTNU环境下的调试工具-FPGA-based embedded CPU card, contains code and testing procedures, as well as in UBUTNU environment of debugging tools
Platform: | Size: 63488 | Author: 辰星和月 | Hits:

[VHDL-FPGA-Verilog] 32位CPU IVERILOG源码

Description: 介绍在FPGA中如何实现32位CPU涉及到额 IVERILOG源码(Describes how to implement 32 bit CPU in FPGA, involving the amount of IVERILOG source code)
Platform: | Size: 76800 | Author: WaaDee | Hits:

[VHDL-FPGA-Verilog] 自己动手写CPU

Description: ? Code文件夹提供了本书每一章涉及的OpenMIPS源代码、测试程序。 ? Tools文件夹提供了GNU工具链的安装文件，以及一个小工具Bin2Mem.exe，该工具用来将二进制数文件转化为可以用于ModelSim仿真的格式。 ? Doc文件夹提供了本书使用的一些IP核的说明手册，包括UART控制器、SDRAM控制器、GPIO模块等。还提供了FPGA开发平台DE2的说明手册。(Code folder Provides the OpenMIPS source code and test program for each chapter of this book. Tools folder Provides an installation file for the GNU tool chain, and a small tool called Bin2Mem.exe that converts binary number files into formats that can be used for ModelSim emulation. Doc folder Some manuals for IP kernel are provided in this book, including UART controller, SDRAM controller, GPIO module and so on. An instruction manual for the FPGA development platform, DE2, is also provided.)
Platform: | Size: 93768704 | Author: 灰太狼的初恋 | Hits:

[Communication-Mobile] FPGA_ASIC-DSP和FPGA共用FLASH进行配置的方法

Description: 通过ASIC、DSP、CPU对FPGA进行配置(Through the ASIC, DSP and CPU on the FPGA configuration)
Platform: | Size: 176128 | Author: xiaohu111 | Hits:

« 12 3 4 5 6 7 8 9 10 »

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[Documents] FPGA_ASIC-基于同步原则的FPGA-CPU设计.rar

[DSP program] TMS320C54x DSP 的cpu和外围设备

[Other] VHDL-FPGA-clock

[VHDL-FPGA-Verilog] cpu-leon3-altera-ep1c20

[Internet-Network] FPGACPU

[VHDL-FPGA-Verilog] lab80

[VHDL-FPGA-Verilog] CPU

[VHDL-FPGA-Verilog] cpu

[VHDL-FPGA-Verilog] cpu

[VHDL-FPGA-Verilog] CPU-Altera-FPGA

[VHDL-FPGA-Verilog] soc-gr0040-010309

[VHDL-FPGA-Verilog] lariviere2008uclinux

[Software Engineering] CPU_Architecture

[Software Engineering] FPGA-cpu

[VHDL-FPGA-Verilog] Convolution_filter-fpga

[Other] FPGA-CPU-DIY

[VHDL-FPGA-Verilog] base-on-FPGA-cpu-

[VHDL-FPGA-Verilog] 32位CPU IVERILOG源码

[VHDL-FPGA-Verilog] 自己动手写CPU

[Communication-Mobile] FPGA_ASIC-DSP和FPGA共用FLASH进行配置的方法

CodeBus www.codebus.net