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Description: Xilinx－ISE辅助设计工具的中文使用说明，包括IP核生成器，布局布线器，FPGA底层编辑器，时序分析器，集成化逻辑分析工具，功率分析工具-Xilinx-ISE-aided design tools for use in Chinese, including the IP core generator, layout router, FPGA Editor bottom, timing analyzer, integrated logic analysis tools, power analysis tools
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Size: 1589248 |
Author: joan |
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Description: 实现了vga的功能，采用文本编辑的，源代码，有利于初学者对FPGA上部分模板学习-Achieved a vga function, using a text editor, source code, help for beginners to learn on the FPGA on the part of the template
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Size: 1024 |
Author: ad |
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Description: 实现了lcd1602显示的功能，可以在lcd上显示“年”字，有利于初学者学习lcd在fpga上显示，采用文本编辑的，利用quartus ii 702-Achieved lcd1602 display function, you can lcd display " " The word will help beginners learn lcd display in the fpga, using a text editor, using quartus ii 702
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Size: 191488 |
Author: ad |
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Description: Advanced Xilinx FPGA
Design with ISE
Objectives
Describe Virtex™ -II advanced architectural features and how they can be used to
improve performance
• Create and integrate cores into your design flow using the CORE Generator™ System
• Describe the different ISE options available and how they can be used to improve
performance
• Describe a flow for obtaining timing closure with Advance Timing Constraints
• Use FloorPlanner to improve timing
• Reduce implementation time with Incremental Design Techniques and Modular Design
Techniques
• Reduce debugging time with FPGA Editor
• On-Chip Verification with ChipScope Pro-Advanced Xilinx FPGA
Design with ISE
Objectives
Describe Virtex™ -II advanced architectural features and how they can be used to
improve performance
• Create and integrate cores into your design flow using the CORE Generator™ System
• Describe the different ISE options available and how they can be used to improve
performance
• Describe a flow for obtaining timing closure with Advance Timing Constraints
• Use FloorPlanner to improve timing
• Reduce implementation time with Incremental Design Techniques and Modular Design
Techniques
• Reduce debugging time with FPGA Editor
• On-Chip Verification with ChipScope Pro
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Size: 10615808 |
Author: rakesh |
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Description: Xilinx ISE软件使用实例
Foundation入门
参数编辑
设计管理器/设计流程向导
FPGA editor
底层编辑器(floorplanner)
硬件调试器（hardware debuger)
JTAG编程（JTAG Programmer)
LogiBLOX
Xilinx FPGA设计进阶
FPGAexpress的使用
Vertex器件结构
层次设计和同步电路设计
HDL设计
时间参数
底层编辑-Xilinx ISE Software Foundation started an instance parameter editing Design Manager/Design Flow Wizard underlying FPGA editor editor (floorplanner) hardware debugger (hardware debuger) JTAG programming (JTAG Programmer) LogiBLOX Xilinx FPGA designs using advanced FPGAexpress hierarchy of Vertex device design and synchronization circuit design parameters of the underlying HDL design time editing
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Size: 5903360 |
Author: lurker |
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Description: Quartus II was a development tool of CPLD / FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: available schematic, block diagram, VerilogHDL, AHDL and VHDL complete circuit description which save it as a design entity documents, chip (circuit) connection layout editor, LogicLock design method, the user can create and optimize the system, and then add the original system which is smaller or no effect on the performance of the follow-up module, powerful logic synthesis tool, complete The logic circuit functional simulation and timing simulation tools, Timer / Time Series Analysis and critical path analysis which can use SignalTap II embedded logic analysis tool for logical analysis-Quartus II was a development tool of CPLD/FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: available schematic, block diagram, VerilogHDL, AHDL and VHDL complete circuit description which save it as a design entity documents, chip (circuit) connection layout editor, LogicLock design method, the user can create and optimize the system, and then add the original system which is smaller or no effect on the performance of the follow-up module, powerful logic synthesis tool, complete The logic circuit functional simulation and timing simulation tools, Timer/Time Series Analysis and critical path analysis which can use SignalTap II embedded logic analysis tool for logical analysis
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Size: 202752 |
Author: jay |
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Description: fpga video for fuse two image and compare the feature
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Size: 7845888 |
Author: black |
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Description: 本论文设计的任意波形发生器所要实现的基本功能：
(1)输出波形的种类：正弦波、方波、三角波、锯齿波、脉冲波、手绘任意波形、任意公式波形。
(2)输出波形每一通道的频率、幅值、偏置都可以由用户调节，并且可以设置多个通道信号之间的相位差。
(3)编辑波形的方式有：设置参数、输入公式、手工绘制通信波特率的全部功能在PC机上实现。
-In this thesis, the arbitrary waveform generator to achieve the basic functions: (1) the type of output waveform: sine, square, triangle wave, sawtooth, pulse, arbitrary waveform hand, any formula waveform. (2) The output waveform of each channel' s frequency, amplitude, offset can be adjusted by the user, and you can set the phase difference between multiple-channel signal. (3) the way the waveform editor: set parameters, enter the formula, hand-painted communication baud rate of the PC, all functions in the implementation.
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Size: 589824 |
Author: loutao |
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Description: 用户将使用具有局部重配置能力的ISE 12.1，进行综合HDL模块并完成设计。之后，使用PlanAhead12.1来布局规划设计，并内部调用执行和分析工具，包括：调用FPGA Editor查看设计实现 调用Constraint Editor创建时序约束；用Timing Analyzer进行时序分析。最后，用户可以用XUPV5开发板来进行硬件验证，并用iMPACT软件来下载全局和局部比特流。-Top-level design dynamically reconfigurable, static logic design with the design of each module and quickly achieve design
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Size: 2048 |
Author: 许飞 |
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Description: 自己下载的dw8051核，并在atlys fpga开发板上运行成功。其中rom和ram都已经生成，4个并行I/O口也有。编程语言是verilog。另外，还有hex转in文件的小软件，以及Uedit这个文本编辑器，它是用来给dw8051的rom载入程序的。-The the dw8051 nuclear, download and run atlys fpga development board. Rom and ram have been generated, there are four parallel I/O port. The programming language is verilog. In addition, there are small software to the hex turn in documents, and Uedit text editor, it is used to dw8051 rom loaded program.
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Size: 29199360 |
Author: ayading826 |
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