Search - FPGA g

[ELanguage] shuma

Description: 7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是2进制的，所以输出表达都是16进制的，为了满足16进制数的译码显示，最方便的方法就是利用VHDL译码程序在FPGA或CPLD中实现。本项实验很容易实现这一目的。例6-1作为7段BCD码译码器的设计，输出信号LED7S的7位分别接如图6-1数码管的7个段，高位在左，低位在右。例如当LED7S输出为 \"1101101\" 时，数码管的7个段：g、f、e、d、c、b、a分别接1、1、0、1、1、0、1，接有高电平的段发亮，于是数码管显示“5”。
Platform: | Size: 206096 | Author: 张龙 | Hits:

[Other resource] work3CNT4BDECL7S

[ELanguage] shuma

Description: 7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是2进制的，所以输出表达都是16进制的，为了满足16进制数的译码显示，最方便的方法就是利用VHDL译码程序在FPGA或CPLD中实现。本项实验很容易实现这一目的。例6-1作为7段BCD码译码器的设计，输出信号LED7S的7位分别接如图6-1数码管的7个段，高位在左，低位在右。例如当LED7S输出为 "1101101" 时，数码管的7个段：g、f、e、d、c、b、a分别接1、1、0、1、1、0、1，接有高电平的段发亮，于是数码管显示“5”。-err
Platform: | Size: 205824 | Author: 张龙 | Hits:

[VHDL-FPGA-Verilog] arm10_verilog

Description: arm10_verilog.rar是基于arm10的verilog代码，对学习和理解 arm10的工作原理和做基于verilog的FPGA开发有帮助。-arm10_verilog.rar is based on the ARM10
Platform: | Size: 25600 | Author: houlongting | Hits:

[VHDL-FPGA-Verilog] work3CNT4BDECL7S

Description: 7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
Platform: | Size: 82944 | Author: lkiwood | Hits:

[VHDL-FPGA-Verilog] RGBtoYCbCr

Description: 采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件. -FPGA realization of the use of color space conversion RGB to Y CbCr of VHDL and Verilog source code, to support a variety of Xilinx devices.
Platform: | Size: 411648 | Author: Jackson | Hits:

[SCM] analysisvoltagesystem

Description: 摘要:电压监测仪的校验工作量大、效率和精度低，为保证电压监测仪性能指标，研制了一种对单相电压监测统计仪进行精度、灵敏度、谐波、时间试验的校验装置。装置以高速单片机为核心，利用丰富的P C机资源、融合F P G A 技术、点阵图形液晶等技术，实现监测仪误差校验过程的自动控制、微机数据管理、程控操作、故障保护。实验结果表明装置综合误差为0 . 1 级，输出电压失真度小于0 . 5 ，系统运行准确、数据传输可靠、操作方便及功能完善。-Abstract: The voltage monitor calibration heavy workload, efficiency and accuracy of low-voltage monitoring device in order to ensure performance indicators, developed a single-phase voltage monitoring of statistical instrument accuracy, sensitivity, harmonic, time calibration test device . Devices to high-speed single-chip microcomputer as the core, the use of PC-rich resources, integration of FPGA technology, dot-matrix graphic LCD and other technologies, monitor implementation of error checking process, automatic control, computer data management, program-controlled operation, fault protection. The results show that the device General error 0.1, the output voltage distortion of less than 0.5 , system operation is accurate, reliable data transmission, easy to operate and function.
Platform: | Size: 455680 | Author: linfeng | Hits:

[VHDL-FPGA-Verilog] hilbert_transformer_latest.tar

Description: The Hilbert Transform is an important component in communication systems, e.g. for single sideband modulation/demodulation, amplitude and phase detection, etc. It can be formulated as filtering operation which makes it possible to approximate the Hilbert Transform with a digital filter. Due to the non-causal and infinite impulse response of that filter, it is not that easy to get a good approximation with low hardware resource usage. Therefore, different filters with different complexities have been implemented. The detailed discussion can be found in "Digital Hilbert Transformers or FPGA-based Phase-Locked Loops" (http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4629940). The design is fully pipelined for maximum throughput.
Platform: | Size: 1239040 | Author: Arun | Hits:

[Communication] AnFPGASoftwareDefinedUltraWidebandTransceiver

Description: Increasing interest in ultra-wideband (UWB) communications has engendered the need for a test bed for UWB systems. An FPGA-based software-defined radio provides both postfabrication definition of the radio and ample parallel processing power. This thesis presents the FPGA design for a software-defined radio targeted to impulse ultra-wideband signals. The system is capable of an effective sampling frequency of up to 8 G-samples/s using timeinterleaved sampling with eight 1-GHz ADCs. The system is also capable of transmitting UWB pulses using a transmitter board controlled by the FPGA. In this thesis, the FPGA design used to capture and export data from the eight ADCs is presented, along with two systems which make use of the transceiver: a pilot-based matched filter communications system, and a remote vital signs monitor.
Platform: | Size: 1396736 | Author: chaiwat | Hits:

[VHDL-FPGA-Verilog] gtp

Description: 一个可以使用的RocketI/O开发实例。基于Xilinx FPGA Virtex5平台。-One can use RocketI/O development example. Based on Xilinx FPGA Virtex5 platform.
Platform: | Size: 2825216 | Author: lyd | Hits:

[SCM] LCD-Display-Driver-Design

Description: ：为了将液晶显示器( L C D) 用于军用设备和一些特殊领域，采用工, _ l k N ． F P G A, ~片，自行设计L C D显示驱动逻辑，研制一种能够可靠工作于． 4 0 ～ + 6 5 ℃的L C D显示驱动器。该显示驱动器能够接收隔行扫描诵视曩信号。逝待去隔行和缩放处理。买现清聚显示。簧通过蔷低温头验o-: For the liquid crystal display (LCD) used in military equipment and some special areas, the use of workers, _ lk N. FPGA, ~ piece, self-designed LCD display drive logic, the development of a reliably working on. 4 0 ~+ 6 5 ℃ of the LCD display driver. The display driver can receive, as in former times chanting interlaced signal. Passed away to be de-interlacing and scaling processing. Buy now clear poly display. The first inspection by Qiang cold spring o
Platform: | Size: 157696 | Author: ads1_2 | Hits:

[VHDL-FPGA-Verilog] digitron_driver_VHD

Description: 关于easy fpga开发板的led数码管的驱动； --输入：控制端ctrl_digin[2:0]共三位，表示（0~7）控制8个数码管的选通， -- 数据端dig_dtin[3:0]共四位，表示（0~F）控制数码管显示的数字 -- 控制时钟clk_dig一位用于时钟同步 --输出：显示dig_dtout[6:0]共七位，控制A,B,C,D,E,F,G[6:0]小数点不包括在内； -- 控制位ctrl_digout[7:0]共八位，任意时刻只能有一个为高，即只有一个数码管显示，为共阳极的； --要求：输入信号：ctrl_digin，dig_dtout,clk_dig一定要稳定-On easy fpga development board led digital tube-driven - Input: Control side ctrl_digin [2:0] a total of three, that (0 to 7) control 8 digital strobe, - Data terminal dig_dtin [3:0] a total of four, said (0 ~ F) control the number of digital display - Control the clock for clock synchronization clk_dig a - Output: Displays dig_dtout [6:0] a total of seven, control A, B, C, D, E, F, G [6:0] decimal point is not included - Control bits ctrl_digout [7:0] of eight, at any time only one high that only a digital display, for a total of anode - Requirements: Input signal: ctrl_digin, dig_dtout, clk_dig must be stable
Platform: | Size: 1024 | Author: 陈伟峰 | Hits:

[VHDL-FPGA-Verilog] digitron_driver_V

Description: 关于easy fpga开发板的led数码管的驱动；此为verilog程序 --输入：控制端ctrl_digin[2:0]共三位，表示（0~7）控制8个数码管的选通， -- 数据端dig_dtin[3:0]共四位，表示（0~F）控制数码管显示的数字 -- 控制时钟clk_dig一位用于时钟同步 --输出：显示dig_dtout[6:0]共七位，控制A,B,C,D,E,F,G[6:0]小数点不包括在内； -- 控制位ctrl_digout[7:0]共八位，任意时刻只能有一个为高，即只有一个数码管显示，为共阳极的； --要求：输入信号：ctrl_digin，dig_dtout,clk_dig一定要稳定-On easy fpga development board led digital tube-driven This is a verilog program - Input: Control side ctrl_digin [2:0] a total of three, that (0 to 7) control 8 digital strobe, - Data terminal dig_dtin [3:0] a total of four, said (0 ~ F) control the number of digital display - Control the clock for clock synchronization clk_dig a - Output: Displays dig_dtout [6:0] a total of seven, control A, B, C, D, E, F, G [6:0] decimal point is not included - Control bits ctrl_digout [7:0] of eight, at any time only one high that only a digital display, for a total of anode - Requirements: Input signal: ctrl_digin, dig_dtout, clk_dig must be stable
Platform: | Size: 1024 | Author: 陈伟峰 | Hits:

[VHDL-FPGA-Verilog] qi-duan-yi-ma-qi

Description: 七段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是2进制的，所以输出表达都是16进制的，为了满足16进制数的译码显示，最方便的方法就是利用译码程序在FPGA\CPLD中来实现。本实验作为7段译码器，输出信号LED7S的7位分别是g、f、e、d、c、b、a，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别为1、1、0、1、1、1、0、1。接有高电平段发亮，于是数码管显示“5”。-Seven-Segment is a pure combinational circuit, usually small-scale special IC, such as 74 or 4000 Series devices only for decimal BCD decoding, digital systems, however data processing and operations are binary, so the output expression hexadecimal, in order to meet the decoding of the hex number display, the most convenient way is to use a decoding program to implement in the FPGA \ CPLD. In this study, as a 7-segment decoder, the output signal LED7S 7 g, f, e, d, c, b, a, high in the left, low on the right. For example, when LED7S output for " 1101101" digital tube 7 paragraph g, f, e, d, c, b, a, respectively 1,1,0,1,1,1,0,1. Access the high level segment shiny, so the digital display " 5" .
Platform: | Size: 3072 | Author: xuling | Hits:

[Other Embeded program] SPI_FPGA

Description: 基于f p g a的s p i借口设计,很有用的-Based on the fpga spi excuse design, useful
Platform: | Size: 32768 | Author: 杨选学 | Hits:

[Special Effects] Most-new-VGA-timing-standards

Description: 最新 V G A 时序标准，对FPGA编写VGA驱动有帮助-Most new V G A timing standards for the preparation of FPGA VGA driver help
Platform: | Size: 613376 | Author: liang | Hits:

[VHDL-FPGA-Verilog] VGA_display_picture

Description: 实现基于 f p g a 的图像处理(Realization of image processing based on FPGA)
Platform: | Size: 19348480 | Author: 布列塔尼 | Hits:

[VHDL-FPGA-Verilog] FPGA黑金开发板AX301原理图

Description: 掌握 V e r i l o g H D L 语言需要的不只是技术而已，最重要是那颗安静的心，安静的心会带读者乘风破浪，一方通行。此外记录笔记的习惯更为重要，向自己学习比起向他人学习更有学习的价值。(It is not only the skill that is required to hold V e r I l o g H D l, but the most important thing is the quiet heart, the quiet heart will take the reader in the wind to break the waves, and the one side will pass.The habit of recording and recording is more important, and it is more valuable to learn from him than to learn from him.)
Platform: | Size: 117760 | Author: 你四哥 | Hits:

[VHDL-FPGA-Verilog] WhiteBalance_10bit

Description: 模块功能：通过白平衡消除由光照带来色差（绿雾）模块输入：亮度增益输出R,G,B三通道像素值（double）模块输出：白平衡后R,G,B三通道像素值（double）(Module function: to eliminate chromatic aberration (green fog) caused by illumination through white balance. Module input: brightness gain output R, G, B three channel pixel value (double) Module output: white balance after R, G, B three channel pixel value (double))
Platform: | Size: 1024 | Author: Andy1123 | Hits:

[Other] 用FPGA实现ATM信元的字头处理_邹扬真

Description: 本文探讨了采用F P G A X 3 0 0 o 系列芯片实现独立于承载码流结构的A T M 信元字头处理器的可能性. 针对F P G A 处理速度相对低于可能的承载码流速率的问题. 着重研究了字头H E C 字段生成、扰码、信元定界、解扰等过程的并行处理算法
Platform: | Size: 422681 | Author: shandongtou | Hits:

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[ELanguage] shuma

[Other resource] work3CNT4BDECL7S

[ELanguage] shuma

[VHDL-FPGA-Verilog] arm10_verilog

[VHDL-FPGA-Verilog] work3CNT4BDECL7S

[VHDL-FPGA-Verilog] RGBtoYCbCr

[SCM] analysisvoltagesystem

[VHDL-FPGA-Verilog] hilbert_transformer_latest.tar

[Communication] AnFPGASoftwareDefinedUltraWidebandTransceiver

[VHDL-FPGA-Verilog] gtp

[SCM] LCD-Display-Driver-Design

[VHDL-FPGA-Verilog] digitron_driver_VHD

[VHDL-FPGA-Verilog] digitron_driver_V

[VHDL-FPGA-Verilog] qi-duan-yi-ma-qi

[Other Embeded program] SPI_FPGA

[Special Effects] Most-new-VGA-timing-standards

[VHDL-FPGA-Verilog] VGA_display_picture

[VHDL-FPGA-Verilog] FPGA黑金开发板AX301原理图

[VHDL-FPGA-Verilog] WhiteBalance_10bit

[Other] 用FPGA实现ATM信元的字头处理_邹扬真

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