Welcome![Sign In][Sign Up]
Location:
Search - FPGA line o

Search list

[VHDL-FPGA-Verilogde2sound

Description: 这个设计结合音频输入从麦克风和线路信号和输出结果线输出信号。麦克风连接话筒端口、音源线在端口,扬声器/耳机线端口。-This design combines audio input from the microphone and line in signals and outputs the result to the line out signal. Connect a microphone to the MIC port, an audio source to the LINE IN port, and speakers/headphones to the LINE OUT port.
Platform: | Size: 105472 | Author: 胡伟 | Hits:

CodeBus www.codebus.net