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Description: 无沦是用离散逻辑、可编程逻辑，还是用全定制硅器件实现的任何数字设计，为了成功地操
作，可靠的时钟是非常关键的。设计不良的时钟在极限的温度、电压或制造工艺的偏差情况下将
导致错误的行为，并且调试困难、花销很大。 在设计PLD/FPGA时通常采用几种时钟类型。时钟可
分为如下四种类型：全局时钟、门控时钟、多级逻辑时钟和波动式时钟。多时钟系统能够包括上
述四种时钟类型的任意组合。-without the expense of discrete logic, programmable logic, or a full-custom silicon device of any digital design, in order to successfully operate, reliable clock is very critical. The poor design of the clock, the limits of temperature, voltage or manufacturing process of the deviation would lead to wrong behavior, and debugging difficulties, costing much. The design PLD/FPGA usually use several types clock. The clock can be divided into the following four types : global clock, clock gating, multi-level logic clock and volatility clock. Multi-clock system to include the above four types of arbitrary clock portfolio.
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Size: 402432 |
Author: 与言 |
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Description: 该文阐述了现场可编程逻辑器件FPGA的主要特点，应用FPGA芯片和VHDL硬件描述语言设计的模拟示波器数字信号显示系统的设计原理和设计方法。-this paper, the field programmable logic devices FPGA main feature FPGA chip and VHDL hardware description language design analog signals to digital oscilloscope system design principles Design and Methods.
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Size: 439296 |
Author: 张志华 |
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Description: 关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
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Size: 179200 |
Author: 李中伟 |
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Description: FPGA逻辑设计，vhdl/verilog altera/xilinx 介绍-FPGA logic design, vhdl/verilog altera/xilinx Introduction
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Size: 2041856 |
Author: zhang |
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Description: 夏宇闻著作：从算法设计到硬线逻辑的实现,讲解比较详细，是一本不错的参考资料-XIA Yu-Wen book: from algorithm design to achieve hard-wired logic to explain in more detail, is a good reference
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Size: 833536 |
Author: HENRRY |
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Description: 基于51和FPGA的逻辑分析仪设计
用C语言编写程序和用VHDL编写硬件程序设计-ａｙｒｅｙｅｙｒｅｙｒｅａｅｙａｙａｙａｙ
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Size: 433152 |
Author: 丁威 |
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Description: 基于FPGA的数字频率计的设计11利用VHDL 硬件描述语言设计,并在EDA(电子设计自动化) 工具的帮助下,用大规模可编程逻辑器件(FPGA/ CPLD) 实现数字频率计的设计原理及相关程序-FPGA-based design of digital frequency meter 11, the use of VHDL hardware description language design, and EDA (electronic design automation) tools with the help of large-scale programmable logic devices used (FPGA/CPLD) digital frequency meter and the design principle related procedures
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Size: 665600 |
Author: 董晨晨 |
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Description: In this chapter we will study the basic structures of FPGAs, known as fabrics.
We will start with a brief introduction to the structure of FPGA fabrics. However,
there are several fundamentally different ways to build an FPGA. Therefore, we
will discuss combinational logic and interconnect for the two major styles of
FPGA: SRAM-based and antifuse-based. The features of I/O pins are fairly simi-
lar among these two types of FPGAs, so we will discuss pins at the end of the
chapter.
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Size: 388096 |
Author: Frank |
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Description: Verilog based 8 bit ALU module, implemented on Spartan 3E FPGA.
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Size: 9216 |
Author: ifusmell |
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Description: 考虑到只基于单片机的频率测量计设计主要是以单片机为基础，原理简单，但由于自身精度问题，测量的范围小。而基于FPGA和单片机结合的频率测量设计主要是以单片机作为系统的主控部件，FPGA完成对时序逻辑控制、计数功能，能较好的利用了FPGA的高精度、高速等方面的优势。-Taking into account only single-chip based on the frequency meter is based on single-chip design based on a simple principle, but because of their precision, the scope of measuring small. And single-chip FPGA-based integrated design of frequency measurement system based on single-chip microcomputer as the main components, FPGA logic control completion of the timing, counting function, can be a better use of FPGA high-precision, high-speed, etc. advantage.
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Size: 261120 |
Author: xiang |
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Description: 基于现场可编程逻辑器件（FPGA）使用VHDL语言QuartusII实现UART通讯-Based on field programmable logic device (FPGA) using VHDL language QuartusII achieve UART communications
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Size: 14336 |
Author: 刘磊 |
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Description: fpga制作的逻辑分析仪 nios2控制系统 自己的科创论文 绝对有用-produced fpga logic analyzer control system nios2 Branch' s own record is absolutely useful papers
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Size: 5821440 |
Author: scarlet |
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Description: NI 通过LabVIEW FPGA 模块和可重复配置I/O(RIO)硬件设备，为测量和控制系统中整合FPGA 技术的
灵活性提供了直观且现成可用的解决方案。您可以使用LabVIEW图形化编程定义FPGA 芯片上的逻辑
功能，您不需要任何的有关底层硬件描述语言(HDLs)的知识，如VHDL 或是Verilog，也不需要了解板
卡级硬件设计，就可以将FPGA 芯片嵌入到NI 可重复配置I/O 系列硬件目标当中。另外，LabVIEW还
可以让您轻松地集成图象采集/分析、运动控制，以及CAN 和RS232 等工业通信功能。-Through the LabVIEW FPGA Module and NI reconfigurable I/O (RIO) hardware device, for measurement and control systems integrate the flexibility of FPGA technology provides the intuitive and readily available solution. You can use the LabVIEW graphical programming custom FPGA logic functions on a chip, you do not need any of the underlying hardware description languages (HDLs) knowledge, such as VHDL or Verilog, do not need to understand the board-level hardware design, it can be FPGA chip embedded into the NI reconfigurable I/O family of hardware Goals. In addition, LabVIEW also allows you to easily integrate image capture/analysis, motion control, as well as CAN and RS232 communication industries.
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Size: 274432 |
Author: 侯yl |
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Description: FPGA算法教程经典! (其中包含加法器,乘 极其算术逻辑部件设计) software engineering 软件工程-FPGA algorithm tutorial. Classic! (Which includes adder, an arithmetic logic unit designed to take the most) software engineering project software
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Size: 1019904 |
Author: 米多 |
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Description: 基于FPGA的步进电机细分控制器的设计。以EDA技术为核心、在可编程逻辑器件上进行系统芯片集成的新设计方法-Segment FPGA-based stepper motor controller design. With EDA technology as the core, in the programmable logic device on the system-chip integration of new design method
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Size: 275456 |
Author: 金 |
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Description: Altera fpga设计基础篇，介绍了公司的一些器件，以及可编程逻辑设计的基本知识-Altera fpga Design Basics, the company introduced a number of devices, and basic knowledge of programmable logic design
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Size: 22090752 |
Author: 章剑 |
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Description: FPGA应用开发入门与典型实例 代码
FPGA（现场可编程逻辑器件）以其体积小、功耗低、稳定性高等优点被广泛应用于各类电子产品的设计中。本书全面讲解了FPGA系统设计的背景知识、硬件电路设计，硬件描述语言Verilog HDL的基本语法和常用语句，FPGA的开发工具软件的使用，基于FPGA的软核嵌入式系统，FPGA设计的基本原则、技巧、IP核， FPGA在接口设计领域的典型应用，FPGA＋DSP的系统设计与调试，以及数字变焦系统和PCI数据采集系统这两个完整的系统设计案例。
-FPGA Application Development and Typical examples of code for FPGA (field programmable logic device) for its small size, low power consumption, high stability, the advantages are widely used in the design of electronic products. This book comprehensively explained the background FPGA system design, hardware design, hardware description language Verilog HDL syntax and basic common statement, FPGA use of the software development tools, FPGA-based soft-core embedded systems, FPGA design of the basic principles , skills, IP core, FPGA interface design field in a typical application, FPGA+ DSP system design and debug, and digital zoom systems and PCI data acquisition system design of two cases of complete system.
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Size: 10980352 |
Author: 海到无涯 |
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Description: FPGA逻辑设计注意事项， 这是一个在逻辑设计中注意事项列表，由此引起的错误常使得设计不可靠或速度较慢，为了提高设计性能和提高速度的可靠性，必须确定设计通过所有的这些检查。-FPGA logic design considerations, this is a note in the list of logical design, which often makes the design errors caused by unreliable or slow, in order to improve design performance and reliability of speed, the design must be determined by all of these Check.
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Size: 5120 |
Author: 张小琛 |
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Description: 该文件包含了FPGA逻辑设计实验的相关代码，提供了ISE平台下可直接运行的代码-This file contains the FPGA logic design experiments related code, provides the code can be run directly under the ISE platform
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Size: 3100672 |
Author: 欧蛟 |
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Description: FPGA常用逻辑的Verilog HDL语言实现，实用的FPGA开发参考资料。(Verilog HDL programming methods of common FPGA logic)
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Size: 1229824 |
Author: ts_ear
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