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Description: actel A3P250 fpga用VERILOG HDL语言实现串口功能的源代码
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Size: 533137 |
Author: wuqj |
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Description: actel A3P250 fpga用VERILOG HDL语言实现串口功能的源代码-actel A3P250 fpga with VERILOG HDL Serial functional language source code
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Size: 533504 |
Author: wuqj |
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Description: Tcode is in VERILOG HDL (Hardware description language)
code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA-Tcode is in VERILOG HDL (Hardware description language)
code is of UART (universal asynchronous receiver&transmitter) receiver . its objective is to accept serial data from port of computer and allow it to come in a FPGA
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Size: 1024 |
Author: hassan |
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Description: quartus.exe 环境下经过编辑和仿真之后,作为FPGA器件的实验用串口接收数据驱动。
-quartus.exe edited and policy environment after the experiment as the FPGA device to receive data-driven serial port.
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Size: 1024 |
Author: |
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Description: FPGA与计算机通信的串口接收程序,用于与计算机或者其他FPGA通信-receive process of FPGA of serial communication, to communicate with computer and other FPGAs
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Size: 1024 |
Author: |
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Description: 用VHDL语言实现的Uart串口通信程序。在xilinx公司FPGA芯片验证过。-Uart serial communication program using VHDL. Validation in xilinx Company FPGA chip.
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Size: 2048 |
Author: 窦斌斌 |
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Description: 在Xilinx的SP605开发板上实现了FPGA接收数据的串口通讯,接收数据是Led会亮,没有接收数据的时候灯是灭的。-Xilinx SP605 development board FPGA receives serial data communication receive data Led lights not receive data when the lights are off.
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Size: 256000 |
Author: 曹荣丽 |
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Description: FPGA实现串口接收功能 Verilog语言-Serial reception FPGA Verilog language
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Size: 3272704 |
Author: 果粒橙 |
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Description: UART FPGA串口发送程序,已经调试通过,可以放心使用,谢谢,(Serial transmission program, has been debugged, can be assured to use, thank you)
Platform: |
Size: 1024 |
Author: dylan025 |
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