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[Software Engineering] firfpga

Description: 在利用FPGA实现数字信号处理方面，分布式算法发挥着关键作用，与传统的乘积-积结构相比，具有并行处理的高效性特点。详细研究了基于FPGA、采用分布式算法实现FIR数字滤波器的原理和方法，并通过Xilinx ISE在Modelsim下进行了仿真。 -FPGA using digital signal processing, distributed algorithm plays a key role with the traditional product-plot structure compared with the efficient parallel processing features. Based on a detailed study of the FPGA, using distributed algorithm FIR digital filter method and the principle, and through the Xilinx ISE under the Modelsim simulation.
Platform: | Size: 228801 | Author: yaoming | Hits:

[VHDL-FPGA-Verilog] firfpga

Description: 在利用FPGA实现数字信号处理方面，分布式算法发挥着关键作用，与传统的乘积-积结构相比，具有并行处理的高效性特点。详细研究了基于FPGA、采用分布式算法实现FIR数字滤波器的原理和方法，并通过Xilinx ISE在Modelsim下进行了仿真。 -FPGA using digital signal processing, distributed algorithm plays a key role with the traditional product-plot structure compared with the efficient parallel processing features. Based on a detailed study of the FPGA, using distributed algorithm FIR digital filter method and the principle, and through the Xilinx ISE under the Modelsim simulation.
Platform: | Size: 228352 | Author: yaoming | Hits:

[VHDL-FPGA-Verilog] s3esk_rotary_encoder_interface

Description: Xilix spartan 3E 旋转编码器接口,脉冲方向识别,AB脉冲滤波 Rotary Encoder Interface Demonstrates how to use the rotary encoder portion of the rotary pushbutton switch.-Xilix spartan 3E rotary encoder interface, pulse direction identification, AB pulse filter Rotary Encoder InterfaceDemonstrates how to use the rotary encoder portion of the rotary pushbutton switch.
Platform: | Size: 279552 | Author: weihua yuan | Hits:

[matlab] filter

Description: 这是基于MATLAB下的XILINX的FPGA的FIR滤波器的模型设计文件-This is a MATLAB-based FPGA of the XILINX Model of the FIR filter design documents
Platform: | Size: 268288 | Author: xueanxi | Hits:

[3G develop] src

Description: DQPSK modulation with XILINX FPGA. 2 level butterworth analog filter for I & Q D/A output. -DQPSK modulation with XILINX FPGA. 2 level butterworth analog filter for I & Q D/A output.
Platform: | Size: 60416 | Author: youker | Hits:

[VHDL-FPGA-Verilog] FIR_filters_Xilinx

Description: FIR filter design method using Xilinx FPGA platform.
Platform: | Size: 1805312 | Author: neorome | Hits:

[VHDL-FPGA-Verilog] sobel

Description: SOBEL FILTER IN VHDL
Platform: | Size: 1024 | Author: Randa | Hits:

[VHDL-FPGA-Verilog] reload_fir

Description: 这是我在Xilinx公司的FPGA上实现的FIR滤波器，调用的内部核，其特色是可以用较少的资源实现该功能，而且可以实现参数重载，即从外部MCU设置FIR滤波器的参数-This is my Xilinx FPGA to achieve the FIR filter, called internal audit, its characteristics can be achieved with fewer resources to this function, and the overload parameters can be achieved, that is, from an external MCU to set the parameters of FIR Filter
Platform: | Size: 16727040 | Author: 林寒风 | Hits:

[VHDL-FPGA-Verilog] FILTRO_DIGITAL_EN_VHDL

Description: DIGITAL FILTER IN VHDL FOR XILINX FPGA SPARTAN 3
Platform: | Size: 2398208 | Author: cesarchirri | Hits:

[VHDL-FPGA-Verilog] Xilinx-FIR

Description: 基于Xilinx FPGA实现的系数可装载数字滤波器源代码-Configurable Digital Filter Based on FPGA (using Verilog under Matlab 2008a)
Platform: | Size: 3090432 | Author: 胡文静 | Hits:

[Software Engineering] DesignandFPGAImplementationof

Description: In most cases, a bandpass filter characteristic is obtained by using a lowpass-to-bandpass frequency transformation on a known lowpass transfer function. This frequency transformation controls the location of passband edges and transfer zero frequencies completely. Using the “Vlach-Chebyshev approximation” [1] however, we are able to specify the (Chebyshev) passband limits directly, together with a free choice of transfer zero locations in the stopband. In this way it is possible to design bandpass transfer functions that cannot be obtained from lowpass functions by a frequency transformation. We think this method to be the only (and not very well known) analytical method to obtain such bandpass characteristics. We show how we designed wave digital realizations from the specification, through a VHDL description and synthesis into a Xilinx FPGA (Virtex-II).
Platform: | Size: 195584 | Author: rakesh | Hits:

[matlab] cdma2k_ddc_12_1

Description: matlab simulink 开发的CDMA2K DDC数字下变频器和滤波器，使用XILINX FPGA V5系列，并包含DDC每个阶段的输出验证matlab程序，非常实用。-matlab simulink developed CDMA2K DDC digital down converter and filter, using the XILINX FPGA V5 series, and contains the output of each stage of verification DDC matlab program, very useful.
Platform: | Size: 33792 | Author: helon | Hits:

[VHDL-FPGA-Verilog] FPGA-multiplier-on-chip

Description: 典型实例11.5 FPGA片上硬件乘法器的使用 软件开发环境：ISE 7.1i 硬件开发环境：红色飓风II代－Xilinx版 本实例实现一个IIR滤波器，并在ISE里面进行仿真。 \rtl目录里面是源文件 \project目录里面是工程-Typical examples 11.5 FPGA chip hardware multiplier using the software development environment: ISE 7.1i hardware development environment: red hurricane II generation-Xilinx version instance to achieve an IIR filter, simulation in ISE inside. \ Rtl directory source files \ project directory project
Platform: | Size: 1111040 | Author: jarod | Hits:

[VHDL-FPGA-Verilog] fir_test

Description: 采用xilinx进行的FPGA的FIR滤波器设计-Conducted using xilinx FPGA FIR filter design
Platform: | Size: 1033216 | Author: 张兴 | Hits:

[VHDL-FPGA-Verilog] dsp_core_tx_filter

Description: 应用在USRP N210上的XIlinx的FPGA开发板上面的变采样滤波器，实现25--30.72M的变采样滤波器，适应LTE物理层的要求-Application on the USRP N210 FPGA development board above XIlinx variable sampling filter, to achieve 25- 30.72M variable sampling filter, adapt LTE physical layer requirements
Platform: | Size: 3072 | Author: 何中华 | Hits:

[VHDL-FPGA-Verilog] filter_2d

Description: XILINX ISE FILE FOR FPGA IMPLIMENTATION OF 2D FIR FILTER USING MODIDIED BOOTH ALGORITHM
Platform: | Size: 1642496 | Author: gsp | Hits:

[VHDL-FPGA-Verilog] 好-无线通信FPGA设计-Xilinx

Description: 《无线通信FPGA设计》以Xilinx公司的FPGA开发平台为基础，综合FPGA和无线通信技术两个方向，通过大量的FPGA开发实例，较为详尽地描述了无线通信中常用模块的原理和实现流程，包括数字信号处理基础、数字滤波器、多速率信号处理、数字调制与解调、信道编码、系统同步、自适应滤波算法、最佳接收机，以及WCDMA系统的关键技术。《无线通信FPGA设计》概念明确、思路清晰，追求全面、系统、实用，使读者能够在较短的时间内具备无线通信领域的FPGA开发能力。(The design of wireless communication FPGA is based on the development platform of Xilinx's FPGA and combines the two directions of FPGA and wireless communication technology. Through a large number of examples of FPGA development, the principle and implementation process of common modules in wireless communication are described in detail, including the basis of digital signal processing, digital filter and multi-rate signal. Processing, digital modulation and demodulation, channel coding, system synchronization, adaptive filtering algorithm, optimal receiver, and key technologies of WCDMA system. The concept of Wireless Communication FPGA Design is clear, and the idea is clear. It pursues comprehensiveness, system and practicality, so that readers can have the ability to develop FPGA in the field of wireless communication in a relatively short time.)
Platform: | Size: 11018240 | Author: 无线电之家99 | Hits:

[Other] Comparative study of FFA architectures using different multiplier and adder topologies

Description: Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm (FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder, carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is used to implement the proposed designs in VHDL.
Platform: | Size: 1123027 | Author: nalevihtkas | Hits:

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