Search - FPGA--DDS-PhaseMeasur

[VHDL-FPGA-Verilog] FPGA-CPLD_DesignTool(5-6)

Description: FPGA-CPLD_DesignTool(example5-6),需要的朋友可以下载-FPGA-CPLD_DesignTool (example5-6), a friend in need can be downloaded
Platform: | Size: 377856 | Author: 磊 | Hits:

[Software Engineering] FPGA_DDS

Description: 基于FPGA＋DDS的MSK数字调制源设计通信中的DDS技术应用-FPGA+ DDS MSK modulation source design communication of DDS technology
Platform: | Size: 115712 | Author: liujl | Hits:

[VHDL-FPGA-Verilog] key

Description: 一个4*4矩阵键盘的VERILOG接口程序设计（FPGA）-A 4* 4 matrix keyboard interface program Verilog Design (FPGA)
Platform: | Size: 199680 | Author: 林虎 | Hits:

[VHDL-FPGA-Verilog] dds_quicklogic

Description: 这是quicklogic公司的直接频率合成（DDS）Verilog代码-QuickLogic Corporation This is a direct frequency synthesizer (DDS) Verilog code
Platform: | Size: 22528 | Author: jinzhoulang | Hits:

[SCM] DDs

Description: 此为DDS的单片机程序，已经得以实现，请放心。-This is the single-chip DDS procedures, has been able to realize, please rest assured.
Platform: | Size: 1024 | Author: 李旸 | Hits:

[assembly language] EXPT84_DAC2ADC

Description: FPGA+DA转换,ALTERA公司FPGA与DA实现,DA转换功能!-FPGA+ DA conversion, ALTERA company FPGA and DA realize, DA conversion!
Platform: | Size: 16384 | Author: 19820521 | Hits:

[Embeded-SCM Develop] NIosIIStart

Description: NIosII软处理器快速入门,ALTERA FPGA的NIOSII入门指导-Quick Start NIosII soft processor, ALTERA FPGA s NIOSII Getting Started guide
Platform: | Size: 617472 | Author: leedong | Hits:

[Other] fenping

Description: FPGA里面的分频器相关资料-FPGA divider inside information
Platform: | Size: 690176 | Author: 11 | Hits:

[SCM] DDS-320-func

Description: 在采用 320x240 屏的设计实验箱上运行，产生正弦波，调幅调频波形，扫频。
Platform: | Size: 460800 | Author: hangyinli | Hits:

Description: dds信号发生器，可以产生任意频率的正弦波，发波和谐波.已经编译通过-dds signal generator, can generate any frequency of the sine wave, the waves and harmonics. has been compiled through
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS的频率转换可以以近似认为是即时的，这是因为它的相位序列在时间上是离散的，在频率控制字改变之后，要经过一个时钟周期之后才能按照新的相位增量增加，所以也可以说它的频率转换时间就是频率控制字的传输时间，-DDS frequency conversion can be considered similar to real-time, this is because it is the phase sequence in time is discrete, in the frequency control word change after one clock cycle to go through before a new phase in accordance with the incremental increase, so it can be said of the frequency switching time is the frequency control word transmission time,
Platform: | Size: 2096128 | Author: lqb | Hits:

[Software Engineering] dds

Description: 基于FPGA的双路可移相任意波形发生器 Altera中国大学生电子设计文章竞赛获奖作品刊登-FPGA-based dual phase shifter can be arbitrary waveform generator Altera China Undergraduate Electronic Design Contest winning entries published articles
Platform: | Size: 1695744 | Author: 姜兆刚 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: DDS原理介绍，里面是有时序图和系统设计！-DDS principle that there is a timing diagram and system design!
Platform: | Size: 454656 | Author: dragon | Hits:

[Software Engineering] dds

Description: dds移相信号发生器 VHDL语言代码-dds
Platform: | Size: 384000 | Author: hanoi | Hits:

[VHDL-FPGA-Verilog] 32_hottest_forum_CPLD-FPGA

Description: 收集了目前关于FPGA设计的论坛，大家如果有什么疑问，可以到这些论坛上求助。-The collection of the current design of the forum on the FPGA, there is little doubt if the U.S. can go to for help on these forums.
Platform: | Size: 13312 | Author: 张芸 | Hits:

[VHDL-FPGA-Verilog] dds

Description: dds算法的fpga实现 altera 根据不同设置，输出不同频率的信号源-dds algorithm to achieve fpga set according to different altera, the output of the signal source at different frequencies
Platform: | Size: 1086464 | Author: liulei | Hits:

[VHDL-FPGA-Verilog] FPGA-basedhigh-performance32-bitfloating-pointnucl

Description: 基于FPGA的高性能32位浮点FFTIP核的开发，适合fpga工程技术人员参考-FPGA-based high-performance 32-bit floating-point nuclear FFTIP development, engineering and technical personnel for reference fpga
Platform: | Size: 7507968 | Author: bonjour | Hits:

[VHDL-FPGA-Verilog] DDS

Description: Quartus中实现的DDS 使用的是altera提供的IP core-DDS achieved Quartus using IP core provided by altera
Platform: | Size: 83968 | Author: ray | Hits:

[Special Effects] VIDEO-FPGA

Description: 视频采集输出实例，FPGA视频采集和输出-Video Capture output examples
Platform: | Size: 6034432 | Author: 王刚 | Hits:

[Software Engineering] FPGA

Description: 为了满足科研与实验需要,提出并实现了一种以FPGA和高速D/A为核心,其结构简单,控制灵活,信号质量高的多功能信号源生成系统。该信号源生成系统能够实时产生中心频率在30~130 MHz的各种雷达、通信、导航和白噪声等信号,且产生的各种信号频率、幅度、相位和其他参数均可控。信号源作为基带信号单元配以混频模块,可实现在任意频段的信号。另外,该信号源还可以作为一个通用平台,通过FPGA内部程序的更新来实现其他复杂信号。-This paper presents and makes a multi-functional signal source based on FPGA and high speed D/A which has simple configuration,flexible controlling,and top-quality signals to satisfy needs of the scientific research and experiment.This signal source can generate several signals as radar signals,communication signals,navigation signals,noise signals and so on.These signals have center frequency between 30~130 MHz,its frequency,power,phase and other parameters are adjustable.This signal source can also ...
Platform: | Size: 330752 | Author: 将建 | Hits:

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[VHDL-FPGA-Verilog] FPGA-CPLD_DesignTool(5-6)

[Software Engineering] FPGA_DDS

[VHDL-FPGA-Verilog] key

[VHDL-FPGA-Verilog] dds_quicklogic

[SCM] DDs

[assembly language] EXPT84_DAC2ADC

[Embeded-SCM Develop] NIosIIStart

[Other] fenping

[SCM] DDS-320-func

[VHDL-FPGA-Verilog] ddswase

[VHDL-FPGA-Verilog] DDS

[Software Engineering] dds

[VHDL-FPGA-Verilog] DDS

[Software Engineering] dds

[VHDL-FPGA-Verilog] 32_hottest_forum_CPLD-FPGA

[VHDL-FPGA-Verilog] dds

[VHDL-FPGA-Verilog] FPGA-basedhigh-performance32-bitfloating-pointnucl

[VHDL-FPGA-Verilog] DDS

[Special Effects] VIDEO-FPGA

[Software Engineering] FPGA

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