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[Other resource] Freq_counter DL : 1: 本代码介绍了使用VHDL开发FPGA的一般流程，最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL，在软件开发平台ISE上完成，可以在较高速时钟频率（100MHz）下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真，并完成了综合布局布线，最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.
Update : 2008-10-13 Size : 502.82kb Publisher : 许的开
[Other resource] freq_counter DL : 0: PIC16F628A芯片制作的频率计
Update : 2008-10-13 Size : 35.82kb Publisher : 朱黄生
[VHDL-FPGA-Verilog] Freq_counter DL : 0: 本代码介绍了使用VHDL开发FPGA的一般流程，最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL，在软件开发平台ISE上完成，可以在较高速时钟频率（100MHz）下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真，并完成了综合布局布线，最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.
Update : 2025-02-17 Size : 503kb Publisher : 许的开
[SCM] freq_counter DL : 0: PIC16F628A芯片制作的频率计-PIC16F628A chip produced Cymometer
Update : 2025-02-17 Size : 36kb Publisher : 朱黄生
[SCM] freq_counter DL : 0: 等精度频率计，用Xilinx FPGA和51单片机实现-Precision frequency meter, etc., using Xilinx FPGA and 51 MCU
Update : 2025-02-17 Size : 395kb Publisher : cx
[VHDL-FPGA-Verilog] freq_counter(Verilog) DL : 0: 数字频率计FPGA代码，用verilog语言实现。-Digital frequency meter FPGA code with verilog language.
Update : 2025-02-17 Size : 425kb Publisher : 郭志东
[SCM] freq_counter DL : 0: Counter with LCD - frecventzmeter
Update : 2025-02-17 Size : 36kb Publisher : liviu
[VHDL-FPGA-Verilog] freq_counter DL : 0: vhdl编写的数字频率计,可用三个频段选择，Quartus II 8.1上测试通过-the frequence counter by VHDL，compiled by Quartus II
Update : 2025-02-17 Size : 8.47mb Publisher : 侯松岩
[Other] Freq_counter DL : 0: 用51单片机测试频率，采样定时器及中断，测试精准。（压缩文件中带仿真图及程序）-With 51 test frequency, sampling timer and interrupt the test precision. (Compressed file with simulation diagram and procedures)
Update : 2025-02-17 Size : 97kb Publisher : 黄忠
[Embeded-SCM Develop] FreqCounter_1_12 DL : 0: 计数本程序是用于访问空间大于 64 KB （即：地址指针数大于两个字节）外部扩展随机存取存储器的源程序文件。(Freq_Counter the procedures for accessing space is greater than 64 KB (ie : Address indicator greater than 2 bytes) of external expansion of random access memory source files.)
Update : 2025-02-17 Size : 8kb Publisher : MMOOMM