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Description: SystemC片上系统设计的源代码：
书籍介绍：
SystemC是被实践证明的优秀的系统设计描述语言，它能够完成从系统到门级、从软件到硬件、从设计到验证的全部描述。SystemC 2.01已作为一个稳定的版本提交到IEEE，申请国际标准。
本书为配合清华大学电子工程系SystemC相关课程的教学而编写。全书分9章，内容包括：硬件描述语言的发展史；SystemC出现的历史背景和片上系统设计方法学概述；SystemC的基本语法；SystemC的寄存器传输级设计和SystemC的可综合语言子集，以及根据作者设计经历归结的RTL设计准则和经验；接口、端口和通道等SystemC行为建模实例——片上总线系统；SystemC与VHDL/Verilog HDL的比较；SystemC的验证标准和验证方法学；SystemC开发工具SystemC_win、WaveViewer等，以及使用MATLAB进行SystemC算法模块的验证。每一章都精心编写了课后习题以配合教学的需要。
本书可作为大学电子设计自动化（EDA）相关课程教材，也可供电子工程技术人员作为SystemC设计、应用开发的技术参考书。本书丰富的实例源代码特别适合初学者根据内容实际运行、体会，举一反三，以掌握SystemC进行应用系统设计。 -SystemC system on chip design source : books introduced : SystemC has been proven in practice is an excellent system design description language, it can be completed from the system level to the door, from hardware to software, from design to verification of all description. SystemC has 2.01 as a stable version submitted to the IEEE, the application of international standards. The book to tie in electronic engineering at Tsinghua University SystemC related courses and preparation of teaching. Book nine chapters, including : hardware description language development history; SystemC is the historical background and system-on-chip design methodology outlined; SystemC basic grammar; SystemC register-transfer-level design and synthesis of SystemC language subset, as well as design experience b
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Size: 2640735 |
Author: c.li |
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Description: 利用EDA工具和硬件描述语言（HDL），根据产品的特定要求设计性能价格比高的片上系统，是目前国际上广泛使用的方法。与传统的设计方法不同，在设计开始阶段并不一定需要具体的单片微控制器（MCU）和开发系统(仿真器)以及带有外围电路的线路板来进行调试，所需要的只是由集成电路制造厂家提供的用HDL描述的MCU核和各种外围器件的HDL模块。设计人员在EDA工具提供的虚拟环境下，不但可以编写和调试汇编程序，也可以用HDL设计、仿真和调试具有自己特色的快速算法电路和接口，并通过综合和布线工具自动转换为电路结构，与制造厂家的单元库、宏库及硬核对应起来，通过仿真验证后，即可投片制成专用的片上系统（SOC)集成电路。-use of EDA tools and hardware description language (HDL), According to the specific requirements of product design to the high cost performance system on a chip, which is widespread international use. With the traditional method, in the beginning stages of the design does not necessarily require specific single-chip microcontroller (MCU) and system development (simulator) and the band with the external circuit to circuit boards for debugging, needed is the IC manufacturers for the use of the HDL description MCU nuclear and various external devices HDL module. Design EDA tools in the virtual environment, it will not only prepare the compilation and debugging procedures, can also use the HDL design, simulation and debugging with its own characteristics, rapid algorithm and interface circuit,
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Size: 18911 |
Author: lilin |
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Description: A practical guide for designing ,synthesizing and simulating ASICs and FPGA using VHDL and verilog hdl
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Size: 1472502 |
Author: zxj0903 |
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Description: SystemC片上系统设计的源代码：
书籍介绍：
SystemC是被实践证明的优秀的系统设计描述语言，它能够完成从系统到门级、从软件到硬件、从设计到验证的全部描述。SystemC 2.01已作为一个稳定的版本提交到IEEE，申请国际标准。
本书为配合清华大学电子工程系SystemC相关课程的教学而编写。全书分9章，内容包括：硬件描述语言的发展史；SystemC出现的历史背景和片上系统设计方法学概述；SystemC的基本语法；SystemC的寄存器传输级设计和SystemC的可综合语言子集，以及根据作者设计经历归结的RTL设计准则和经验；接口、端口和通道等SystemC行为建模实例——片上总线系统；SystemC与VHDL/Verilog HDL的比较；SystemC的验证标准和验证方法学；SystemC开发工具SystemC_win、WaveViewer等，以及使用MATLAB进行SystemC算法模块的验证。每一章都精心编写了课后习题以配合教学的需要。
本书可作为大学电子设计自动化（EDA）相关课程教材，也可供电子工程技术人员作为SystemC设计、应用开发的技术参考书。本书丰富的实例源代码特别适合初学者根据内容实际运行、体会，举一反三，以掌握SystemC进行应用系统设计。 -SystemC system on chip design source : books introduced : SystemC has been proven in practice is an excellent system design description language, it can be completed from the system level to the door, from hardware to software, from design to verification of all description. SystemC has 2.01 as a stable version submitted to the IEEE, the application of international standards. The book to tie in electronic engineering at Tsinghua University SystemC related courses and preparation of teaching. Book nine chapters, including : hardware description language development history; SystemC is the historical background and system-on-chip design methodology outlined; SystemC basic grammar; SystemC register-transfer-level design and synthesis of SystemC language subset, as well as design experience b
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Size: 2640896 |
Author: c.li |
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Description: 利用EDA工具和硬件描述语言（HDL），根据产品的特定要求设计性能价格比高的片上系统，是目前国际上广泛使用的方法。与传统的设计方法不同，在设计开始阶段并不一定需要具体的单片微控制器（MCU）和开发系统(仿真器)以及带有外围电路的线路板来进行调试，所需要的只是由集成电路制造厂家提供的用HDL描述的MCU核和各种外围器件的HDL模块。设计人员在EDA工具提供的虚拟环境下，不但可以编写和调试汇编程序，也可以用HDL设计、仿真和调试具有自己特色的快速算法电路和接口，并通过综合和布线工具自动转换为电路结构，与制造厂家的单元库、宏库及硬核对应起来，通过仿真验证后，即可投片制成专用的片上系统（SOC)集成电路。-use of EDA tools and hardware description language (HDL), According to the specific requirements of product design to the high cost performance system on a chip, which is widespread international use. With the traditional method, in the beginning stages of the design does not necessarily require specific single-chip microcontroller (MCU) and system development (simulator) and the band with the external circuit to circuit boards for debugging, needed is the IC manufacturers for the use of the HDL description MCU nuclear and various external devices HDL module. Design EDA tools in the virtual environment, it will not only prepare the compilation and debugging procedures, can also use the HDL design, simulation and debugging with its own characteristics, rapid algorithm and interface circuit,
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Size: 18432 |
Author: lilin |
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Description: 基于Altera公司系列FPGA(Cyclone EP1C3T144C8)、Verilog HDL、MAX7219数码管显示芯片、4X4矩阵键盘、TDA2822功放芯片及扬声器等实现了《电子线路设计• 测试• 实验》课程中多功能数字钟实验所要求的所有功能和其它一些扩展功能。包括：基本功能——以数字形式显示时、分、秒的时间，小时计数器为同步24进制，可手动校时、校分；扩展功能——仿广播电台正点报时，任意时刻闹钟（选做），自动报整点时数（选做）；其它扩展功能——显示年月日（能处理大月小月，可手动任意设置年月日），秒表（包括开始、暂停和清零）。-based Altera FPGA series (Cyclone EP1C3T144C8) , Verilog HDL, MAX7219 Digital Display chips, 4x4 matrix keyboard, TDA2822 chip power amplifier and loudspeakers of the "Electronic Circuit Design
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Size: 23552 |
Author: 田世坤 |
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Description: < 大型RISC处理器设计--用描述语言Verilog设计VLSI芯片>>光盘-<Large RISC processor design- Verilog design language used to describe VLSI chip>> CD-ROM
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Size: 874496 |
Author: wiyn |
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Description: 摘 要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间
显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示
了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优
化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。
关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ-Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ
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Size: 211968 |
Author: 杨轶帆 |
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Description: 主要介绍了等精度频率测量原理，该原理具有在整个测试频段内保持高精度频率
测量的优点 同时在该原理基础上，采用了Verilog HDL语言设计了高速的等精度测频
模块，并且利用EDA开发平台QUARTUS11 3 .0对CPLD芯片进行写人，实现了计数等
主要逻辑功能 还使用C语言设计了该等精度频率计的主控程序以提高测量精度。本设
计实现了对频率变化范围较大的信号进行频率测量，能够满足高速度、高精度的测频要
求。-Introduced, such as the accuracy of frequency measurement principle, the principle has in the entire test frequency to maintain the advantages of high precision frequency measurement at the same time the basis of the principle of using the Verilog HDL language, such as the design of a high-speed precision frequency measurement module, and use of EDA Development platform QUARTUS11 3 .0 on CPLD chip to write, and achieved a count of the main logic function, such as the use of C language is also designed such precision the frequency of control procedures to enhance measurement accuracy. This design achieved a wide range of frequency changes in signal frequency measurement, to meet the high-speed, high precision frequency measurement requirements.
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Size: 320512 |
Author: zhengwei |
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Description: 利用QuartusII的"MegaWizard Plug-In Manager",
设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE
把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行
时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。
2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_COUNTER，
设计一个20bit的up_only COUNTER,
要求该COUNTER在FE0FA和FFFFF之间自动循环计数；
分析该COUNTER在EPM7128SLC84-7、EPM7128SLC84-10、和EPF10K70RC240-2、
EPF10K70RC240-4几种芯片中的最大工作频率；
请将计数器的输出值在FFFFC--FE0FF之间的仿真波形打印出来
（仅EPF10K70RC240-4芯片,最大允许Clock频率下）。-QuartusII use the MegaWizard Plug-In Manager , the design of the input data width is 4bit the ADD, SUB, MULT, DIVIDE, COMPARE them as a project, DEVICE selected EPF10K70RC240-4, on their timing simulation, the simulation waveform (input output selected group) in a paper print out. 2. QuartusII use the MegaWizard Plug-In Manager in LPM_COUNTER, the design of a 20bit of up_only COUNTER, requested that the COUNTER in FE0FA and automatic cycle count between FFFFF analysis of the COUNTER in EPM7128SLC84-7, EPM7128SLC84-10, and EPF10K70RC240-2, EPF10K70RC240-4 Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency).
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Size: 31744 |
Author: 李侠 |
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Description: The emphasis of this book is on real-time application of Synopsys tools, used
to combat various problems seen at VDSM geometries. Readers will be
exposed to an effective design methodology for handling complex, submicron
ASIC designs. Significance is placed on HDL coding styles,
synthesis and optimization, dynamic simulation, formal verification, DFT
scan insertion, links to layout, physical synthesis, and static timing analysis.
At each step, problems related to each phase of the design flow are identified,
with solutions and work-around described in detail. In addition, crucial issues
related to layout, which includes clock tree synthesis and back-end
integration (links to layout) are also discussed at length. Furthermore, the
book contains in-depth discussions on the basics of Synopsys technology
libraries and HDL coding styles, targeted towards optimal synthesis solution.
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Size: 2244608 |
Author: wsea |
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Description: 种用FPGA 实现对高速A/ D 转换芯片的控制电路,系统以MAX125 为例,详细介绍了含有FIFO 存储器的A/ D 采样控制电路的设计方法,并给出了A/D 采样控制电路的V HDL 源程序和整个采样存储的顶层电路原理图.-Species with FPGA to achieve high-speed A/D conversion chip control circuit, the system as an example to MAX125 details FIFO memory contains A/D sampling control circuit design method, and gives the A/D sampling control circuit of the V HDL source code and the sample stored in the top-level circuit schematic.
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Size: 338944 |
Author: 于银 |
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Description: HDL Chip Design - A Practical Guide for Designing Synthesizing and Simulating ASIC and FPGA-HDL Chip Design- A Practical Guide for Designing Synthesizing and Simulating ASIC and FPGA
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Size: 34065408 |
Author: hung ta |
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Description: HDL Chip Design: A Practical Guide for Designing, Synthesizing & Simulating ASICs & FPGAs Using VHDL or Verilog
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Size: 32904192 |
Author: lenam |
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Description: 高科技的发展使芯片设计不再是半导体工业的领域，现场可编程逻辑阵列（FPGA）的出现使通过软件来快速实现芯片设计成为可能。本系统是广泛面向全球的工程技术人员和大专院校学生，使您能够在最短的时间内掌握FPGA的应用与VHDL/AHDL/Verilog HDL这一电子逻辑设计利器，迅速的加入高级电子设计人才行列。-The development of high-tech chip design is no longer the field of semiconductor industry, field programmable logic arrays (FPGA) through the emergence of chip design software to quickly achieve the possible. This system is a broad global engineering and technical personnel and college students, so that you can in the shortest possible period of time to master the application of FPGA and VHDL/AHDL/Verilog HDL logic design of the electronic weapon, quickly adding advanced electronic design talent ranks.
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Size: 258048 |
Author: 童志通 |
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Description: Douglas Smith HDL Chip Design (OCRed)
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Size: 8304640 |
Author: andry_nik |
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Description: 引入了Verilog HDL
硬件描述语言，向读者展示一种九十年代才真正开始在美国等先进的工业国家逐步推广的
数字逻辑系统的设计方法。借助于这种方法，在电路设计自动化仿真和综合工具的帮助下，
我们完全有能力设计并制造出有自己知识产权的DSP（数字信号处理）类和任何复杂的数
字逻辑集成电路芯片，为我国的电子工业和国防现代化作出应有的贡献。-The introduction of the Verilog HDL hardware description language, to show the reader a kind of nineties really began in the United States and other advanced industrial countries to gradually extend the digital logic system design. With this method, simulation and integrated circuit design automation tools help, we are fully capable to design and create their own intellectual property rights of DSP (digital signal processing) and any complex digital logic integrated circuit chip, for our electronic industry and make due contributions to national defense modernization.
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Size: 2217984 |
Author: da liu |
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Description: actel单片机的软FIFO设计和串口通讯程序-actel single chip design soft FIFO and serial communication program
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Size: 4096 |
Author: 欧阳 |
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Description: HDL Chip Design --- A Practical Guide for Designing, Synthesizing & Simulating Asics & Fpgas Using Vhdl or Verilog (EBook)
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Size: 32634880 |
Author: Lawrence |
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Description: 基于FPGA的频率计设计。通过FPGA运用、 HDL编程，利用FPGA(现场可编程门阵列)芯片设计了一个8位数字式等精度频率计，该频率计的测量范围为0-100MHZ，利用QUARTUS II集成开发环境进行编辑、综合、波形仿真，并下载到CPLD器件中，经实际电路测试，仿真和实验结果表明，该频率计有较高的实用性和可靠性。-Frequency counter FPGA-based design. By using FPGA, VHDL programming, the use of FPGA (field programmable gate array) chip design an 8-bit digital precision frequency meter, etc., the frequency meter measurement range of 0-100MHZ, using QUARTUS II integrated development environment for editing, synthesis, simulation waveforms, and downloaded to the CPLD device, the actual circuit testing, simulation and experimental results show that the frequency counter has a higher availability and reliability.
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Size: 595968 |
Author: 吴亮 |
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