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[WEB Code] hdl优化设计十大戒律

Description: hdl优化设计十大戒律-转载-HDL design optimization Ten commandments-reproduced
Platform: | Size: 36260 | Author: 王进 | Hits:

[Documents] hdl优化设计十大戒律

Description: hdl优化设计十大戒律-转载-HDL design optimization Ten commandments-reproduced
Platform: | Size: 35840 | Author: 王进 | Hits:

[VHDL-FPGA-Verilog] Verilog-HDL

Description: 本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子，这些例子全部通过了验证。第七章以后的设计实例，不仅有Verilog-HDL的例子，也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。 -the CD-ROM include "Verilog-HDL Practice and Application System Design," a book the whole Examples of these examples were passed certification. After the seventh chapter, a design example is not only Verilog-HDL example, the report include VB, VC and other source files, even DLL generator also described in detail.
Platform: | Size: 784384 | Author: 东子 | Hits:

[Other] ImplementationFromAlgorithmDesigntoHardwareLogic.r

Description: 第一章 数字信号处理、计算、程序、 算法和硬线逻辑的基本概念 第二章 Verilog HDL设计方法概述 第三章 Verilog HDL的基本语法 第四章 不同抽象级别的Verilog HDL模型 第五章 基本运算逻辑和它们的Verilog HDL模型 第六章 运算和数据流动控制逻辑-the first chapter of digital signal processing and computing procedures, hard-line algorithm and the basic logic of the concept of the second chapter of Verilog HDL design methods outlined in the third chapter Verilo g HDL basic grammar Chapter 4 different levels of abstract Verilog HDL model V basic arithmetic logic and their Verilog HDL model of the sixth chapter operations and data flow control logic
Platform: | Size: 421888 | Author: 陈亨利 | Hits:

[Books] DSP_WITH_FPGA

Description: The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP, as well as HDL design flow, CORE Generator software, and design implementation tools. Through hands-on exercises, you will implement a design from algorithm concept to verification. -The DSP Design Flow workshop provides an introduction to the advanced tools you need to design and implement DSP algorithms targeting FPGAs. This intermediate workshop in implementing DSP functions focuses on learning how to use System Generator for DSP, as well as HDL design flow, CORE Generator software, and design implementation tools. Through hands-on exercises, you will implement a design from algorithm concept to verification.
Platform: | Size: 9935872 | Author: Jawen | Hits:

[Other] Verilog.HDL.A.Guide.To.Digital.Design.And.Synthesi

Description: VHDL的数字设计与综合的经典图书，与大家共享-VHDL digital design and synthesis of the classic books, and share
Platform: | Size: 1723392 | Author: 张三 | Hits:

[VHDL-FPGA-Verilog] shejiVerilogExample

Description: Verilog 程序例子 王金明：《Verilog HDL程序设计教程》程序例子，带说明。 -Verilog procedures guo examples : "Verilog HDL Design Guide" procedures example, take note.
Platform: | Size: 160768 | Author: mingming | Hits:

[VHDL-FPGA-Verilog] chap6

Description: 《Verilog HDL 程序设计教程》3-"Verilog HDL Design Guide" 3
Platform: | Size: 2048 | Author: hutian | Hits:

[Other] Verilog-HDL

Description: 本书从实际的角度介绍了硬件描述语言Verilog-HDL。通过动手实践体验其语法结构、功能等内涵-This book from a practical point of introduction of hardware description language Verilog-HDL. By doing practical experience of its grammatical structure and function of the connotation of
Platform: | Size: 5829632 | Author: 皱接 | Hits:

[VHDL-FPGA-Verilog] SystemOfTaxiFeeBasedOnVerilogHDL

Description: 摘 要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优 化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。 关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ-Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ
Platform: | Size: 211968 | Author: 杨轶帆 | Hits:

[Software Engineering] Veilogbook

Description: 第一章 数字信号处理、计算、程序、算法和硬线逻辑的基本概念 第二章 Verilog HDL设计方法概述 第三章 Verilog HDL的基本语法 第四章 不同抽象级别的Verilog HDL模型 第五章 基本运算逻辑和它们的Verilog HDL模型 第六章 运算和数据流动控制逻辑 第七章 有限状态机和可综合风格的Verilog HDL-The first chapter of digital signal processing, computing, procedures, algorithms and hard-wired logic of the basic concepts of Chapter II Verilog HDL design methods outlined in Chapter III of the basic Verilog HDL syntax in Chapter IV of different abstraction levels of Verilog HDL model of Chapter V of the basic arithmetic logic and Verilog HDL model of their Chapter VI computing and data flow control logic of Chapter VII of the finite state machine and an integrated style of Verilog HDL
Platform: | Size: 1079296 | Author: 碗筷 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 北大微电子学系于敦山老师的课件，介绍Verilog HDL、Cadence Verilog仿真器、可综合的Verilog HDL、设计举例、自动布局布线工具、Verilog的词汇约定等内容-Department of Microelectronics, Peking University in the teacher s courseware mts on Verilog HDL, Cadence Verilog simulator can be integrated Verilog HDL, design, for example, automatic placement and routing tools, Verilog, etc. terms agreed
Platform: | Size: 1550336 | Author: 唐进 | Hits:

[Other] Verilog_HDL_HuaWei_advanced_cours

Description: 这是华为使用的内部培训教程！ 本文主要介绍了Verilog HDL 语言的一些基本知识，目的是使初学者能够迅速掌 HDL 设计方法，初步了解并掌握Verilog HDL语言的基本要素，能够读懂简单的设计代码并 够进行一些简单设计的Verilog HDL建模。-This is Huawei s internal training course to use! This paper mainly introduces the Verilog HDL language, some basic knowledge, the purpose is to enable beginners to quickly charge of HDL design methodology, a preliminary understanding of Verilog HDL language and mastery of the basic elements that can read a simple design code and enough to carry out some simple Verilog design HDL modeling.
Platform: | Size: 263168 | Author: xiaoju | Hits:

[VHDL-FPGA-Verilog] Verilog-HDL

Description: 《Verilog-HDL实践与应用系统设计》一书中的光盘源文件- Verilog-HDL practice and application of system design, a book on CD-ROM source file
Platform: | Size: 771072 | Author: 范田田 | Hits:

[VHDL-FPGA-Verilog] HuaweiFPGAdesignflowguide

Description: 华为内部的FPGA设计培训教程，详细阐述了设计流程图、Verilog HDL设计、逻辑仿真、逻辑综合。对大家的学习一定有帮助的。-Huawei within the FPGA design training tutorial, a detailed flow chart of the design, Verilog HDL design, logic simulation, logic synthesis. Study of the U.S. must have help.
Platform: | Size: 34816 | Author: 张芸 | Hits:

[VHDL-FPGA-Verilog] Verilog_HDL_progamming

Description: Verilog-HDL程序设计实用教程收集，内容丰富，设计技巧多样。-Verilog-HDL Design Tutorial practical collection, rich in content and variety of design skills.
Platform: | Size: 40601600 | Author: liuxing | Hits:

[VHDL-FPGA-Verilog] miaobiao

Description: 用Verilog HDL编写的秒表设计，可以实现百分之一秒，十分之一秒，秒，十秒等功能。-Verilog HDL prepared with a stopwatch designed to achieve the hundredth of a second, one-tenth of seconds, seconds, 10 seconds and other functions.
Platform: | Size: 6144 | Author: maylag | Hits:

[Software Engineering] Advance-HDL-Design-Training-On-Xilinx-FPGA

Description: dvance HDL Design Training On XilinxFPGA thanhmaikmt dao thanh mai
Platform: | Size: 2196480 | Author: DAO THANH MAI | Hits:

[VHDL-FPGA-Verilog] 《Verilog HDL设计与实战》配套代码(1)

Description: 《Verilog HDL设计与实战》配套代码 verilog源程序(Verilog HDL design and actual combat code Verilog source program)
Platform: | Size: 6552576 | Author: 铭铭扬扬 | Hits:

[source in ebook] 《Verilog HDL设计与实战》配套代码（2）

Description: 《Verilog HDL设计与实战》配套代码 (2)("Verilog HDL design and actual combat" matching code (2))
Platform: | Size: 103367680 | Author: 铭铭扬扬 | Hits:
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