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Description: 说明:S3C44B0 BIOS的keil CARM版
源代码来自互连网,由本人进行了一些修改,使其在keil UV3 2.5A上编译通过。
主要修改的地方在启动文件,FLASH的烧录部分,另外在控制台中增加了几个命令。
硬件平台为: CPU:S3C44B0;SDRAM:HY57V641620;FLASH:29LV160DB;网卡芯片:RTL8019AS。
本软件仅供学习交流使用,不得用于其它用途,否则后果自负。
解压密码请用 computer00
更新信息请看:
http://computer00.21ic.org/user1/2198/archives/2007/37838.html-: S3C44B0 BIOS keil amplifier version source code from the Internet. I conducted by some modifications to make them keil UV3 compiled by 2.5A. Major revisions to the commencement of the local paper, the writers of Flash, another increase in the console of several orders. Hardware Platform : CPU : S3C44B0; SDRAM : HY57V641620; FLASH : 29LV160DB; Card Chip : RTL8019AS. The software is for learning to share, should not be used for other purposes, or otherwise bear the consequences themselves. Please extract passwords computer00 updated information, see : http : / / computer00.21ic.org/user1/2198/archive s/2007/37838.html
Platform: |
Size: 70919 |
Author: Liu |
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Description: 44b0X开发板
CPU:S3C44B0X
FLASH:HY29LV160BT 2M
SDRAM:HY57V641620 8M
2 COM
USB1.1 PDIUSBD12
NET RTL8019AS
JTAG 14PIN
LCD 接口
4 KEY-44b0X development board CPU : S3C44B0X FLASH : HY29LV160BT 2M SDRAM : HY57V641620 8M two COM USB1.1 PDIUSBD12 NET RTL80 19AS JTAG interface LCD 14PIN 4 KEY
Platform: |
Size: 987209 |
Author: 邹枫 |
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Description: 动态随即存储器的时序和工作原理,剖析了其运行的状态机,对底层程序开发有帮助(例子是关于HY57V641620)
Platform: |
Size: 431904 |
Author: hlc |
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Description: CPU:S3C44B0X FLASH:HY29LV160BT 2M SDRAM:HY57V641620 8M 2 COM USB1.1 PDIUSBD12 NET RTL8019AS JTAG 14PIN LCD 接口 4 KEY 3 LED 峰鸣器 时钟电池-CPU : S3C44B0X FLASH : 2M SDRAM HY29LV160BT : HY57V641620 8M two COM USB 1.1 PDIUSBD12 NET RTL8019AS JTAG interface LCD 14PIN four LED KEY 3-Wong-clock battery
Platform: |
Size: 1812660 |
Author: 田昊 |
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Description: CPU:S3C44B0X FLASH:HY29LV160BT 2M SDRAM:HY57V641620 8M 2 COM USB1.1 PDIUSBD12 NET RTL8019AS JTAG 14PIN LCD 接口 4 KEY 3 LED 峰鸣器 时钟电池-CPU : S3C44B0X FLASH : 2M SDRAM HY29LV160BT : HY57V641620 8M two COM USB 1.1 PDIUSBD12 NET RTL8019AS JTAG interface LCD 14PIN four LED KEY 3-Wong-clock battery
Platform: |
Size: 1812480 |
Author: 田昊 |
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Description: JTAG CPLD实现源代码,比用简单并口调试器快5倍以上。
以前总觉得简单的并口jtag板速度太慢,特别是调试bootloader的时候,简直难以忍受。最近没什么事情,于是补习了几天vhdl,用cpld实现了一个快速的jtag转换板。cpld用epm7128stc100-15,晶振20兆,tck频率5兆。用sjf2410作测试,以前写50k的文件用时5分钟,现在则是50秒左右。tck的频率还可以加倍,但是不太稳定,而且速度的瓶颈已经不在tck这里,而在通讯上面了。
-JTAG CPLD source code than the simple parallel debugger five times faster. Before feel simple parallel port JTAG board is too slow, especially when debugging Bootloader, simply intolerable. No matter recently, so VHDL tutorial for a few days, with cpld to achieve a rapid conversion of JTAG board. Cpld with epm7128stc100-15, 20 Katherine crystal, the frequency tck 5 trillion. Sjf2410 used for testing, before the document was made with 50k at 5 minutes, now it is about 50 seconds. Tck frequencies can also doubled, but not too stable, but the rate has not tck bottleneck here, and in the above communications.
Platform: |
Size: 2048 |
Author: 李伟 |
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Description: 44b0X开发板
CPU:S3C44B0X
FLASH:HY29LV160BT 2M
SDRAM:HY57V641620 8M
2 COM
USB1.1 PDIUSBD12
NET RTL8019AS
JTAG 14PIN
LCD 接口
4 KEY-44b0X development board CPU : S3C44B0X FLASH : HY29LV160BT 2M SDRAM : HY57V641620 8M two COM USB1.1 PDIUSBD12 NET RTL80 19AS JTAG interface LCD 14PIN 4 KEY
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Size: 1082368 |
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Author: 飞翔 |
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Description: Hynix公司8M byte sdr sdram的verilog语言仿真实现。-Hynix company 8M byte sdr sdram realize the Verilog simulation language.
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Size: 105472 |
Author: 张力 |
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Description: 动态随即存储器的时序和工作原理,剖析了其运行的状态机,对底层程序开发有帮助(例子是关于HY57V641620)-Then the dynamic memory timing and working principle, analyzes the state machine its running on the bottom of program development helpful (example is the HY57V641620)
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Description: SDRAM-HY57V641620中文资料-SDRAM-HY57V641620
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