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[Other resource] ocidec3

Description: IDE的Verilog设计，已经经过验证。
Platform: | Size: 26883 | Author: Jason | Hits:

[Books] VerilogReferenceGuide

Description: verilog语言语法参考书，全英文的，老外的编的，可以作为“枕头了”，适用于有verilog语言编程经验的。 -Verilog language grammar reference books, all in English, a series of the foreigners, as "a pillow," apply to Verilog language programming experience.
Platform: | Size: 203776 | Author: | Hits:

[Embeded-SCM Develop] pwm_source

Description: ALTERA PWM電路 這是一個ALTERA的PWM電路，可以整合到NIOSII IDE中，來完成一個PWM的系統。-Altera PWM circuit Altera This is a PWM circuit, NIOSII can be integrated into the IDE, to complete a PWM system.
Platform: | Size: 11264 | Author: Faye Tung | Hits:

[VHDL-FPGA-Verilog] ocidec3_IDE_controller

Description: 硬盘控制器VHDL源代码，实现了PIO和DMA方式，请支持-hard disk controller VHDL source code and realized the PIO and DMA mode, please support
Platform: | Size: 38912 | Author: 磊 | Hits:

[VHDL-FPGA-Verilog] ocidec3

Description: IDE的Verilog设计，已经经过验证。 -IDE of the Verilog design, has been verified.
Platform: | Size: 26624 | Author: Jason | Hits:

[VHDL-FPGA-Verilog] ide_control

Description: 三段式Verilog的IDE程序，但只有DMA部分，需要自己添加PIO的代码-Verilog three-step procedure of the IDE, but only parts of DMA, PIO required to add their own code
Platform: | Size: 2048 | Author: wang | Hits:

[Linux-Unix] Linux_bc

Description: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[VHDL-FPGA-Verilog] NovakodStudio

Description: For all thoses interested in a new language and programming paradigm. This is a complete IDE for programming in the psC - Parallel and synchronous C- Language. This language is a high level replacement for VHDL/verilog.-For all thoses interested in a new language and programming paradigm. This is a complete IDE for programming in the psC - Parallel and synchronous C- Language. This language is a high level replacement for VHDL/verilog.
Platform: | Size: 15300608 | Author: Luc | Hits:

[VHDL-FPGA-Verilog] pwm

Description: 利用Verilog语言产生17路PWM波，控制17路舵机，可以作为IP核添加到AVALON总线上，在nios IDE里用C语言控制。-Using Verilog language production of 17 Road PWM signal to control 17 Servos, can be used as IP core to the AVALON bus, in the nios IDE in control with the C language.
Platform: | Size: 3072 | Author: 尹长生 | Hits:

[VHDL-FPGA-Verilog] Verilog000

Description: FPGA的学习，熟悉QuartusII软件的各种功能，各种逻辑算法设计，接口模块(RS232,LCD,VGA,SPI,I2c等)的设计，时序分析，硬件优化等，自己开始设计简单的FPGA板子。 ③、NiosII的学习，熟悉NiosII的开发流程，熟悉开发软件(SOPC,NiosII IDE),了解NiosII的基本结构，设计NiosII开发板，编写NiosII C语言程序，调试板子各模块功能。-Verilog语言的学习，熟悉Verilog语言的各种语法。 ②、FPGA的学习，熟悉QuartusII软件的各种功能，各种逻辑算法设计，接口模块(RS232,LCD,VGA,SPI,I2c等)的设计，时序分析，硬件优化等，自己开始设计简单的FPGA板子。 ③、NiosII的学习，熟悉NiosII的开发流程，熟悉开发软件(SOPC,NiosII IDE),了解NiosII的基本结构，设计NiosII开发板，编写NiosII C语言程序，调试板子各模块功能。
Platform: | Size: 22794240 | Author: onejacky | Hits:

[VHDL-FPGA-Verilog] LIP6111CORE_ide_dvd

Description: IDE DVD Verilog Code
Platform: | Size: 4303872 | Author: jc | Hits:

[VHDL-FPGA-Verilog] IDEinterface

Description: IDE接口时序和最全的接口定义，通过它可以实现硬盘的扇区读写-IDE interface timing and the most comprehensive interface definition, it can be achieved by sector hard disk read and write
Platform: | Size: 425984 | Author: wang | Hits:

[VHDL-FPGA-Verilog] IDE_Interface

Description: IDE接口程序，是用VERILOG写的，高手进阶程序-IDE interface program is written using VERILOG, master advanced procedures. .
Platform: | Size: 595968 | Author: wns | Hits:

[VHDL-FPGA-Verilog] Behavioral-Modeling

Description: A Code that illustrates 12 bit switch, 2x1 Mux, 2x4 Decoder in behavioral modeling in Verilog HDL using modelsim IDE
Platform: | Size: 1024 | Author: Asad Abbas | Hits:

[VHDL-FPGA-Verilog] ADD_lab_manual_2K8

Description: This Advance Digital Design Manual, that is taught in our University, it takes from the basic to the advance in Verilog Programming using Modelsim IDE, very good for self learning-This is Advance Digital Design Manual, that is taught in our University, it takes from the basic to the advance in Verilog Programming using Modelsim IDE, very good for self learning
Platform: | Size: 621568 | Author: Asad Abbas | Hits:

[VHDL-FPGA-Verilog] SHA256_SYSTEM

Description: 利用硬件（可编程逻辑器件FPGA）实现密码算法SHA256，在FPGA中嵌入软核NIOSii，在NIOSii上进行软件编程。 硬件EDA工具为ALTERA的Quartus ii，软件IDE为eclipse（嵌在Quartua中）。(The hardware (programmable logic device FPGA) is used to implement the cryptographic algorithm SHA256, and the soft core NIOSii is embedded in the FPGA, and the software is programmed on the NIOSii. The hardware EDA tool is the Quartus II of ALTERA, and the software IDE is eclipse (embedded in Quartua).)
Platform: | Size: 4413440 | Author: 风@筝 | Hits:

[VHDL-FPGA-Verilog] eeprom_test_Verilog

Description: eeprom工程，实现了基本的读写，供参考。工程使用的IDE为“ISE Design Suite 14.7”，使用时可根据自己硬件，修改引脚配置和逻辑可控制。(EEPROM project, the realization of the basic reading and writing for reference. The IDE used in the project is "ISE Design Suite 14.7", which can be used to modify pin configuration and logic control according to its own hardware.)
Platform: | Size: 159744 | Author: shaoyang_v | Hits:

[VHDL-FPGA-Verilog] uart_test_Verilog

Description: 用verilog实现了uart功能的demo工程。工程使用的IDE为“ISE Design Suite 14.7”，使用时可根据自己硬件，修改引脚配置即可。(The demo project of UART function is realized with Verilog. The IDE used in the project is "ISE Design Suite 14.7", which can be used to modify the pin configuration according to its own hardware.)
Platform: | Size: 128000 | Author: shaoyang_v | Hits:

[VHDL-FPGA-Verilog] demodulation

Description: 基于verilog HDL的BPSK解调的FPGA实现，仿真结果验证良好。IDE为vivado 2014( U57FA u4E8Everilog HDL u7684BPSK u89E3 u8C03 u7684FPGA u5B9E u73B0 uFF0C u4EFF u771F u7ED3 u679C u9A8C u8BC1 u826F u597D u3002IDE u4E3Avivado 2014)
Platform: | Size: 131072 | Author: 涛2017777 | Hits:

[VHDL-FPGA-Verilog] cordic

Description: 基于verilog HDL的cordic算法FPGA实现。省去繁琐的乘法开方计算。IDE为vivado 2014( U57FA u4E8Everilog HDL u7684cordic u7B97 u6CD5FPGA u5B9E u73B0 u3002 u7B1 u53BB u7E1 u7410 u7684 u4E58 u6CD5 u5F00 u65B9 u8BA1 u7B97 u300BIDE u4E3Avivado 2014)
Platform: | Size: 97280 | Author: 涛2017777 | Hits:
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