Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - IDEA VHDL

Search list

[Other resource] 单片机坐标定时器实验

Description: http://www.edacn.net/cgi-bin/forums.cgi?forum=7&topic=9127下,则R3～R0的输出信号中会有一个为1,但我们还是是无法确定哪一个键被按下,必須要从R3 ～R0 的输出信号与C3～C0的扫描信号共同決定那个按键被按下. 编写VHDL的构思: 外部接口包括: a. INPUT脚 : CLK , R3～R0. b. OUTPUT脚 : C3～C0 , DATA3～DATA0(辨别出的按键值). -7topic http://www.edacn.net/cgi-bin/forums.cgi forum = = 9127, under R3 R0 to the output signal will be one to one, but we are unable to confirm which a key is pressed, we must proceed from R3 to R0 the output signal C0 to C3 with the scanning signal jointly decided that button is pressed. the idea of the preparation of VHDL : external interfaces include : a. INPUT feet : CLK, R3 ~ R0. b. feet OUTPUT : C0 to C3, DATA3 ~ DATA0 (identify the key values ).
Platform: | Size: 1559994 | Author: 杨要强 | Hits:

[Embeded-SCM Develop] VHDLRAM

Description: 介绍vhdl硬件描述语言的特点及设计思想，运用vhdl硬件描述语言实现计算机原理实验中RAM存储器的设计方法，重点描述了对传统计算机组成原理实验中移植到基于CPLD平台的思想-introduced vhdl hardware description language features and design ideas, vhdl use hardware description language computer science experiments RAM memory design, Description of key computer components of the traditional principle experiment to transplant platform based on the idea of CPLD
Platform: | Size: 30907 | Author: 刘浏 | Hits:

[VHDL-FPGA-Verilog] 单片机坐标定时器实验

Description: http://www.edacn.net/cgi-bin/forums.cgi?forum=7&topic=9127下,则R3～R0的输出信号中会有一个为1,但我们还是是无法确定哪一个键被按下,必須要从R3 ～R0 的输出信号与C3～C0的扫描信号共同決定那个按键被按下. 编写VHDL的构思: 外部接口包括: a. INPUT脚 : CLK , R3～R0. b. OUTPUT脚 : C3～C0 , DATA3～DATA0(辨别出的按键值). -7topic http://www.edacn.net/cgi-bin/forums.cgi forum = = 9127, under R3 R0 to the output signal will be one to one, but we are unable to confirm which a key is pressed, we must proceed from R3 to R0 the output signal C0 to C3 with the scanning signal jointly decided that button is pressed. the idea of the preparation of VHDL : external interfaces include : a. INPUT feet : CLK, R3 ~ R0. b. feet OUTPUT : C0 to C3, DATA3 ~ DATA0 (identify the key values ).
Platform: | Size: 1559552 | Author: 杨要强 | Hits:

[Embeded-SCM Develop] VHDLRAM

Description: 介绍vhdl硬件描述语言的特点及设计思想，运用vhdl硬件描述语言实现计算机原理实验中RAM存储器的设计方法，重点描述了对传统计算机组成原理实验中移植到基于CPLD平台的思想-introduced vhdl hardware description language features and design ideas, vhdl use hardware description language computer science experiments RAM memory design, Description of key computer components of the traditional principle experiment to transplant platform based on the idea of CPLD
Platform: | Size: 30720 | Author: 刘浏 | Hits:

[VHDL-FPGA-Verilog] Pentium

Description: 这两个分别是8位乘法器的VHDL语言的实现，并经过个人用QUARTUS的验证，另外一个是奔腾处理器的设计思想-The two were 8 multiplier realization of VHDL language and personal use Quartus After verification, another is a Pentium processor design idea
Platform: | Size: 378880 | Author: citydremer | Hits:

[Crack Hack] IDEA_EN_TOP

Description: IDEA加密运算模块，运算速率100Mbps，请大家参考-IDEA encryption algorithms module, computing speed 100Mbps, please refer to
Platform: | Size: 4096 | Author: 刘文庆 | Hits:

[Crack Hack] IDEA_DE_TOP

Description: IDEA解密运算模块，运算速率100Mbps，请大家参考-IDEA decryption computing module, computing speed 100Mbps, please refer to
Platform: | Size: 9216 | Author: 刘文庆 | Hits:

[Books] FPGAtaxier

Description: 摘要: 本文介绍了基于FPGA 的出租车计价器系统的功能、设计思想和实现, 该设计采用模块化自上而下的层次化设计,顶 层设计有5 个模块,各模块中子模块采用VHDL 或图形法设计。在Max+plusⅡ下实现编译、仿真等,最后成功下载到FPGA 芯 片中。完成了可预置自动计费、自动计程、计时、空车显示等多功能计价器。由于FPGA 具有高密度、可编程及有强大的软件 支持等特点,所以该设计具有功能强、灵活和可靠性高等特点,具有一定的实用价值。-Abstract: This paper introduces the function, design idea and realization of taximeter based on FPGA. The design takes the method of top-down and step by step. The whole system was divided into five modules that were described by VHDL or schematic diagram. By using Max+plus Ⅱ accomplish the compiler, simulator and so on. And then it can be downloaded to the FPGA chip . Achieve the goal to make a taximeter with the function of automatism count the money, the kilometer, the time and show empty car on a screen, ether. On FPGA high density and Programmable ability, you can see it has function better, modify convenient and high dependability. It has certainly practical value.
Platform: | Size: 206848 | Author: lu | Hits:

[VHDL-FPGA-Verilog] FPGAphaselockedloopdesign

Description: 介绍了应用VHDL技术设计嵌入式全数字锁相环路的方法，详细叙述了其工作原理和设计思想，并用可编程逻辑器件FPGA实现。-Introduce the application of VHDL technical design embedded DPLL road approach, described in detail its working principle and design idea, and programmable logic device FPGA implementation.
Platform: | Size: 286720 | Author: 朱雯 | Hits:

[VHDL-FPGA-Verilog] ideacore1

Description: This is IDEA encryption Algorithm. Tested on Sparton 3 xilinx FPGA.
Platform: | Size: 2048 | Author: bhagwan | Hits:

[VHDL-FPGA-Verilog] VHDL_procedures

Description: VHDL程序来让蜂鸣器发出音乐的声音 这种电路设计要分好几个模块 主要思路是用ROM记录乐谱 然后用分频器分频 还有就是用计数器读取乐谱 另外还可以扩展 使其显示音符 这是一个做好了的 就是ROM没填谱-VHDL procedures are in place to allow the voice of music The buzzer sounded a circuit design that several sub-modules to the main idea is to record music with ROM and then use the frequency divider is also counter to read music to use can be extended also to show notes This is a good ROM没填spectrum is
Platform: | Size: 2048 | Author: yy0838 | Hits:

[VHDL-FPGA-Verilog] Electronic_Calendar_Based_On_FPGA

Description: 本项目主要是利用FPGA技术实现电子日立的功能，显示年月日星期，显示格式为：“年. 月. 日. 星期”，其中年月日星期均为可调电路。该项目共有七个模块：星期控制电路、日期控制电路、月份控制电路、年份控制电路、选择月份电路、扫描显示电路和调节电路。总体思路是：星期和日期控制电路共用一个脉冲信号；日期的进位反馈给调节电路，再通过调节电路中的开关控制选择月份和月份控制电路的脉冲信号，以起到随时调节月份的作用；同理，月份控制电路的进位反馈给调节电路以随时调节年份。-The project is mainly the use of FPGA technology to achieve the functions of e-Hitachi, showing date week display format: "year. On. Day. Weeks", which are adjustable date-week circuit. A total of seven modules of the project: week control circuit, the date of the control circuit, control circuit of the month, year, control circuit, select the month of the circuit, scan display circuit and regulating circuit. The general idea is: the date a week and share a pulse control circuit signal date back to the binary-conditioning circuit, and then by adjusting the switch control circuit to choose the month and the month of the pulse signal control circuit, at any time to play a role in regulation of the month with the rationale for, the month of binary control circuit to adjust the feedback circuit to adjust the year at any time.
Platform: | Size: 43008 | Author: xiaoxu | Hits:

[Other] cpld-pci

Description: 使用 cpld实现pci的功能，思路较为简单方面，希望大家可以测试一下-Use cpld achieve pci functions, a relatively simple idea, the hope that we can test
Platform: | Size: 1024 | Author: tiantian | Hits:

[Software Engineering] taxi

Description: 介绍了出租车计费器系统的组成及工作原理，简述了在EDA平台上用单片CPLD器件构成该数字系统的设计思想和实现过程。论述了车型调整模块、计程模块、计费模块、译码动态扫描模块等的设计方法与技巧。-Introduced a taxi meter system, the composition and working principle outlined in the EDA platform, with the single-chip CPLD devices constitute the digital system design idea and implementation process. Discusses the models to adjust module, the meter module, billing module, decoding module and so dynamic scan design methods and techniques.
Platform: | Size: 153600 | Author: 蒋思 | Hits:

[Other] T4_01_Introduccion_VHDL

Description: HDL fue diseñ ado en base a los principios de la programación estructurada. La idea es definir la interfaz de un modulo de hardware mientras deja invisible sus detalles internos. La entidad (ENTITY) en VHDL es simplemente la declaración de las entradas y salidas de un modulo mientras que la arquitectura (ARCHITECTURE) es la descripción detallada de la estructura interna del modulo o de su comportamiento.
Platform: | Size: 711680 | Author: tor | Hits:

[VHDL-FPGA-Verilog] comparator_4

Description: 基于VHDL的数值比较器，通过此比较器实现思想，可以扩展到更多位的-VHDL-based numerical comparator, the comparator through the implementation of this idea can be extended to more places
Platform: | Size: 278528 | Author: 宋茜 | Hits:

[VHDL-FPGA-Verilog] FPGA_UART

Description: 用Verilog语言实现的FPGA UART独立收发模块 思路简单，代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能：串口收到数据后立即回传，此后每一秒串口数据+1再发送。-Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.
Platform: | Size: 3072 | Author: 朱强光 | Hits:

[VHDL-FPGA-Verilog] moveophone

Description: 移动式的游戏控制器基于vhdl. 简单结构 目前只能识别led-Due to the recent trend in creating devices that allow the playing of games using movement rather than a traditional joystick, controller, or keyboard, we felt that a project that followed this idea would be interesting. This led us to the idea of using movement to control a musical instrument, while removing a physical instrument from the equation.
Platform: | Size: 7315456 | Author: 张洋洋 | Hits:

[Crack Hack] IDEA-decryption-HDL-code

Description: Decryption code for IDEA algorithm in VHDL
Platform: | Size: 24576 | Author: peter pablo | Hits:

[Software Engineering] xilinx-idea-vhdl-master

Description: here I send VHDL code for IDEA algorithm
Platform: | Size: 54272 | Author: qutaiba | Hits:
« 12 »

CodeBus www.codebus.net