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[Other resource] VerilogHDLPLI

Description: Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,
Platform: | Size: 998 | Author: 杨锐 | Hits:

[Other resource] Functional

Description: Basic Test Concepts DC Parameters AC Parameters Functional Parameters Device Characterization Test Program Development Analog Test Concepts Test Using DSP Techniques in Testing Noise Reduction Techniques in Testing -Test Parameters AC DC Param eters Functional Parameters Device Character ization Test Program Development Analog Test C Using DSP oncepts Test Techniques in Testing No. ise Reduction Techniques in Testing
Platform: | Size: 8725247 | Author: 王浩 | Hits:

[Software Engineering] FPGA_GPS_C_A

Description: 本文：采用了FPGA方法来模拟高动态(Global Position System GPS)信号源中的C／A码产生器。C／A码在GPS中实现分址、卫星信号粗捕和精码(P码)引导捕获起着重要的作用，通过硬件描述语言VERILOG在ISE中实现电路生成，采用MODELSIM、SYNPLIFY工具分别进行仿真和综合。
Platform: | Size: 164313 | Author: xiaozhu | Hits:

[VHDL-FPGA-Verilog] VerilogHDLPLI

Description: Verilog HDL的PLI子程序接口，用于与用户C程序在2个方向上传输数据，可用xilinx ISE，quartusii或modelsim仿真，-Verilog HDL PLI subroutine interfaces, for C program with the user in the direction of two transmission of data, available xilinx ISE. quartusii or modelsim simulation,
Platform: | Size: 1024 | Author: 杨锐 | Hits:

[Software Engineering] Functional

Description: Basic Test Concepts DC Parameters AC Parameters Functional Parameters Device Characterization Test Program Development Analog Test Concepts Test Using DSP Techniques in Testing Noise Reduction Techniques in Testing -Test Parameters AC DC Param eters Functional Parameters Device Character ization Test Program Development Analog Test C Using DSP oncepts Test Techniques in Testing No. ise Reduction Techniques in Testing
Platform: | Size: 8724480 | Author: 王浩 | Hits:

[Other] Noise_Reduction

Description: Advanced Digital Signal Processing and Noise Reduction - Second Edition-Advanced Digital Signal Processing and No. ise Reduction-Second Edition
Platform: | Size: 3710976 | Author: happyguy | Hits:

[Software Engineering] FPGA_GPS_C_A

Description: 本文：采用了FPGA方法来模拟高动态(Global Position System GPS)信号源中的C／A码产生器。C／A码在GPS中实现分址、卫星信号粗捕和精码(P码)引导捕获起着重要的作用，通过硬件描述语言VERILOG在ISE中实现电路生成，采用MODELSIM、SYNPLIFY工具分别进行仿真和综合。-This article: FPGA method used to simulate the high dynamic (Global Position System GPS) signal source of the C/A code generator. C/A code in GPS to achieve sub-sites, the satellite signal capture coarse and fine code (P code) lead capture plays an important role, through hardware description language Verilog in ISE to achieve circuit to generate, using MODELSIM, SYNPLIFY simulation tools were and integrated.
Platform: | Size: 163840 | Author: xiaozhu | Hits:

[VHDL-FPGA-Verilog] convert

Description: 用与生成ISE的IP核的COE文件，一些具体的参数要自己设置一下！
Platform: | Size: 1024 | Author: 1111 | Hits:

[Other] ISE_KeilC_ICCAVR_Guide

Description: ISE、Keil C和ICCAVR快速入门指南-ISE, Keil C and ICCAVR Quick Start Guide
Platform: | Size: 690176 | Author: 豆豆 | Hits:

[ARM-PowerPC-ColdFire-MIPS] timer

Description: 用C语言实现在Xlinx公司的FPGA的延时程序在ISE软件编程环境下-With the C language implementation in the Xlinx the company' s FPGA-delay procedures in ISE software programming environments
Platform: | Size: 1024 | Author: Sapphire | Hits:

[Embeded-SCM Develop] ps2

Description: PS2.c - FlashLite186 iç in PS/2 Klavye Fonksiyonlarý */ /* Lima Endustriyel Bilgisayar - www.lima.com.tr */ /* Haziran 2004 - Istanbul, Turkiye */ /* */ /* Konsol, INT2 ve PORTC nin 0 + 1. pinlerini kullaný r */ /* */ /* Klavyenin CLOCK sinyali INT2 ve PORTC nin 0. pinine */ /* DATA sinyali ise PORTC nin 1. pinine bað lý dý r */ /* */ /* Her iki aç ý k kolektö r sinyal 10k luk direnç lerle */ /* 5V a bað lanmý þ tý r- PS2.c - FlashLite186 iç in PS/2 Klavye Fonksiyonlarý */ /* Lima Endustriyel Bilgisayar - www.lima.com.tr */ /* Haziran 2004 - Istanbul, Turkiye */ /* */ /* Konsol, INT2 ve PORTC nin 0 + 1. pinlerini kullaný r */ /* */ /* Klavyenin CLOCK sinyali INT2 ve PORTC nin 0. pinine */ /* DATA sinyali ise PORTC nin 1. pinine bað lý dý r */ /* */ /* Her iki aç ý k kolektö r sinyal 10k luk direnç lerle */ /* 5V a bað lanmý þ tý r
Platform: | Size: 3072 | Author: alinetmo | Hits:

[GUI Develop] pstesth

Description: PS2.c - FlashLite186 iç in PS/2 Klavye Fonksiyonlarý */ /* Lima Endustriyel Bilgisayar - www.lima.com.tr */ /* Haziran 2004 - Istanbul, Turkiye */ /* */ /* Konsol, INT2 ve PORTC nin 0 + 1. pinlerini kullaný r */ /* */ /* Klavyenin CLOCK sinyali INT2 ve PORTC nin 0. pinine */ /* DATA sinyali ise PORTC nin 1. pinine bað lý dý r */ /* */ /* Her iki aç ý k kolektö r sinyal 10k luk direnç lerle */ /* 5V a bað lanmý þ tý r-PS2.c - FlashLite186 iç in PS/2 Klavye Fonksiyonlarý */ /* Lima Endustriyel Bilgisayar - www.lima.com.tr */ /* Haziran 2004 - Istanbul, Turkiye */ /* */ /* Konsol, INT2 ve PORTC nin 0 + 1. pinlerini kullaný r */ /* */ /* Klavyenin CLOCK sinyali INT2 ve PORTC nin 0. pinine */ /* DATA sinyali ise PORTC nin 1. pinine bað lý dý r */ /* */ /* Her iki aç ý k kolektö r sinyal 10k luk direnç lerle */ /* 5V a bað lanmý þ tý r
Platform: | Size: 24576 | Author: alinetmo | Hits:

[SCM] ccd

Description: 高速高分辨率CCD器件的实用化是近年图像采集领域的一个研究热点。选用科学级柯达 新型高分辨率可见光面阵CCD KA I- 0304设计了一种高速图像采集系统。该系统采用KSC - 100作为时序发生器驱动面阵CCD 和信号处理器AD9840A, 实现对CCD面阵输出模拟信号的高速A /D转换, 并将信号快速转存至片外SDRAM 存储器, 经USB 采集系统将数据发送到计算机。系统采用相关双采样( CDS)技术滤除信号中的相关噪声, 提高了系统的信噪比, 采集速度达40Mb it / s, 具有 集成度高、低噪声、数据传输速度快等特点。经测试, 系统工作稳定, 为高端科学级CCD面阵的实用化提供了一种设计方案。-The applicat ion of h igh speed and high reso lution CCD is a research ho tspot in im age ac􀀁 quisit ion fie ld. A high speed image acqu isition system is introduced and designed by using a new high reso lution sc ientific leve l v isible light area CCD KA I- 0304. In the design, area CCD and signa l processor AD9840A are driven by using KSC- 100 as the tim ing and driv ing c ircuit and then the conversion o f h igh speed A /D for the CCD output o f analog signal is performed. The generated data signa l is qu ickly transferred to ex terna l SDRAM m emory. Fina lly, data w ill be sent to a computer via USB acqu isition system. Furthermo re, correlated double sampling( CDS) techno logy is adopted in the sys􀀁 tem to remove the relevant signa l no ise and the signal- to- no ise ration( SNR) is improved. The acqui􀀁 sition speed is up to 40Mbit/s. The system is featured by high integration, low no ise, h igh speed data transm ission. A fter test ing, the s
Platform: | Size: 259072 | Author: 胡 | Hits:

[VHDL-FPGA-Verilog] iselab

Description: ise实验教程，适合初学者学习使用，能够熟悉赛林思FPGA开发环境。-ise experimental tutorial for beginners to learn to use, to become familiar with Sailin Si FPGA development environment.
Platform: | Size: 670720 | Author: hu | Hits:

[VHDL-FPGA-Verilog] Viterbi_verilog

Description: 在ISE环境下用Verilog语言编写的卷积码程序及Viterbi译码程序-Under the ISE Verilog language with procedures and Viterbi convolutional code decoding program
Platform: | Size: 5121024 | Author: lxz | Hits:

[FlashMX] Flash-read-and-write-using-C

Description: 本文档描述了如何利用ISE中软件开发环境SDK进行C编程对FLASH进行读写的方法，免去了自建IP核对flash进行读写的步骤，大大提高了效率-This doc show a method that can read and write flash memory easily using SDK develop environment of ISE. That make it no necessary to develop a IP core by yourself and improve the flash operation efficicy remarkably.
Platform: | Size: 50176 | Author: 欧比 | Hits:

[SCM] Xilinx-ISE

Description: 苏州大学的一部很不错的关于飞思卡尔汽车竞赛的编程语言设计介绍的书-this book is very good book written by professors in Suzhou University,which relates to the design of programing by c/c++.
Platform: | Size: 10620928 | Author: 张鹏 | Hits:

[VHDL-FPGA-Verilog] my_uart2

Description: 基于FPGA的串口通信源代码。已经经过调试助手测试，-Release 13.2- WebTalk (O.61xd) Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. Project Information -------------------- ProjectID=BFC2DD71D6FA404A87FDA640DB4B5999 ProjectIteration=14 WebTalk Summary ---------------- INFO:WebTalk:1- WebTalk is enabled because you are using a WebPACK license. INFO:WebTalk:8- WebTalk Install setting is ON. INFO:WebTalk:6- WebTalk User setting is ON. INFO:WebTalk:5- D:/Xilinxsheji/my_uart2/usage_statistics_webtalk.html WebTalk report has not been sent to Xilinx. Please check your network and proxy settings. For additional details about this file, please refer to the WebTalk help file at D:/xilinx13.2/ISE_DS/ISE/data/reports/webtalk_introduction.html
Platform: | Size: 253952 | Author: chen | Hits:

[Other Embeded program] PCF8583

Description: This file is contains the application PCF8583 RTC There is also the Proteus simulation. Code ise written CCS C compiler. There is also the Proteus simulation.
Platform: | Size: 130048 | Author: mustafa | Hits:

[VHDL-FPGA-Verilog] Xilinx

Description: 2020 XILINX Vivado ISE IP License最全最可靠License获取方式。 LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MAC 50G Enthernet MAC 100G Enthernet MAC RS Encoder/Decoder Display Port/ DP Video Test Pattern Generator RapidIO tri mode ethernet mac(LDPC, CPRI, Turbo, Polar, JESD204B/C HDMI1.4/2.0, MIPI CSI-2, MIPI DSI AXI CAN AXI USB2.0 SD Card Host Reed-Solomon Decoder/Encoder 10G Enthernet MAC 25G Enthernet MAC 40G Enthernet MAC 50G Enthernet MAC 100G Enthernet MAC RS Encoder/Decoder Display Port/ DP Video Test Pattern Generator RapidIO tri mode ethernet mac)
Platform: | Size: 1024 | Author: liyan2020 | Hits:
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