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Description: D触发器和JK触发器，使用emacs编写源文件，iverilog仿真通过，内有png仿真图像截屏-D flip-flop and JK flip-flop, use emacs to prepare source file, iverilog simulation adopted, within the simulation images png screenshots
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Size: 5120 |
Author: 孙斌 |
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Description: 触发器设计范例，JK触发器的VHDL实现-Trigger for example, JK flip-flop of VHDL implementation
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Size: 291840 |
Author: 宋茜 |
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Description: 通过jk触发器实现2进2的EWB程序，直接在EWB环境下运行仿真，快捷方便 -Jk Trigger 2 by 2 into the EWB program, run directly in the EWB simulation environment, fast and convenient
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Size: 7168 |
Author: Frank T |
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Description: 各类触发器VHDL源码程序，在quartus-ii7.2版本上测试通过，文件中包括D触发器，JK触发器，RS触发器，T触发器。-Various triggers VHDL source code program in quartus-ii7.2 version of the test is passed, the document includes a D flip-flop, JK flip-flop, RS flip-flop, T flip-flop.
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Size: 925696 |
Author: baoguocheng |
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Description: 1. clkdiv 介绍时钟分频器的建模
2. counter 介绍计数的建模
3. dtrig 介绍D触发器的建模
4. jktrig 介绍JK触发器的建模
5. shiftreg 介绍移位寄存器的建模
6. ttrig 介绍T触发器的建模-The 1. Clkdiv modeling clock divider 2. Counter introduced count modeling the The 3. Dtrig 4. Jktrig introduce the modeling of the JK flip-flop 5 introduces the D flip-flop modeling. Shiftreg introduces the modeling of shift register 6 the. ttrig T trigger modeling
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Size: 576512 |
Author: 丁俊辉 |
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Description: 基于labviewd可以实现的JK触发器-JK Trigger
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Size: 29696 |
Author: jef |
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Description: 本实验是VHDL的触发器实现，将基本RS触发器，同步RS触发器，集成J-K触发器，D触发器同时集成在一个CPLD芯片中模拟其功能，并研究其相互转化的方法。-This experiment is the trigger of VHDL realize, will be basically RS flip-flop, synchronous RS flip-flop, the integrated JK flip-flop, D flip-flops simultaneously integrated in a CPLD chip to simulate its functionality, and to study their mutual transformation approach.
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Size: 728064 |
Author: 陈芳 |
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Description: 1.八进制计数器
2.八位右移寄存器
3.八位右移寄存器（并行输入串行输出）
4.半加
5.半加器
6.半减器
7.两数比较器
8.三数比较器
9.D触发器
10.T触发器
11.JK1触发器
12.JK触发器
13.三位全加器
14.SR触发器
15.T1触发器
16.三太门
17.有D触发器构成的6位2进制计数器
18.带同步置数的7进制减法计数器（6位右移寄存器）
19.二十四进制双向计数器
20.二选一
21.分频器
22.含同步清零的十进制加计数器
23.或门
24.7段译码器
25.8-3优先编码器
26.32位锁存器
27.八位左移寄存器
28.数据选择器4选1
29.两个三位二进制数全加器
-1 octal counter 2. Eight right register 3. Eight right register (parallel input serial output) 4 and a half plus 5 half adder 6. Half 7. Comparator compares the two numbers 8 Third number is 9.D trigger 10.T trigger 11.JK1 trigger 12.JK trigger 13. three full adder 14.SR trigger 15.T1 trigger 16. three too gate 17 with a D flip-flops 6-bit binary counter 18. 7 binary down counter with synchronous set number (6 right shift register) 19. twenty-four bidirectional binary counter 20. Alternative 21. divider 22. including synchronous clear plus zero decimal counter 23., or 24.7 Doors segment decoder 25.8-3 Priority Encoder 26.32 latch 27. eight left shift register 28. 4 election data selector 129. two three binary full adder implement
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Size: 4096 |
Author: wanghao |
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Description: 设计RS、JK、D、T 四种触发器，掌握异步复位置位的方法以及四种触发功能的实现方
法，掌握QuartusII 软件的使用方法以及GW48 型SOPC 开发平台中的输入输出模式配置方
法。 -Design RS, JK, D, T four kinds of triggers, grasp complex bit asynchronous methods and how to configure four trigger implementation function QuartusII master the use of software and SOPC development platform GW48-type input and output modes.
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Size: 1024 |
Author: 张双图 |
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Description: 用verilog编写的带同步清0、同步置1 的D 触发器；带异步清0、异步 置1 的JK 触发器-Verilog prepared by the synchronous belt, synchronous D flip-flop 0 1 with Asynchronous Clear 0, asynchronous set D trigger 1 with Asynchronous Clear 0, asynchronous set JK trigger 1!!!!!!
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Size: 529408 |
Author: 望奎 |
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Description: 这是一个在quartus2上写好的JK触发器，下载并运行其中quartus文件即可。(This is a JK trigger written on quartus2, downloading and running the quartus file.)
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Size: 7557120 |
Author: 瓜皮233
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