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[mpeg mp3] video_compression_systems

Description: 根据jpeg标准用verilog语言编写的视频编码器，此编码器可作为一个通用IP使用，完成数字音频/视频的编解码功能-under jpeg standards with the Verilog language video encoder, this encoder can be used as a common IP use, complete digital audio / video codec
Platform: | Size: 222770 | Author: 崔云飞 | Hits:

[Compress-Decompress algrithms] jpeg_encoder

Description: 完整的jpeg encoder verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現精簡電路-complete jpeg encoder Verilog code, DCT is partly based on the IEEE 1991 transection paper, using skew circular convolutions to achieve streamlining circuit
Platform: | Size: 25437 | Author: 李寧 | Hits:

[mpeg mp3] video_compression_systems

Description: 根据jpeg标准用verilog语言编写的视频编码器，此编码器可作为一个通用IP使用，完成数字音频/视频的编解码功能-under jpeg standards with the Verilog language video encoder, this encoder can be used as a common IP use, complete digital audio/video codec
Platform: | Size: 222208 | Author: | Hits:

[Compress-Decompress algrithms] jpeg_encoder

Description: 完整的jpeg encoder verilog code,DCT部分採用1991 IEEE transection paper,利用skew circular convolution來實現精簡電路-complete jpeg encoder Verilog code, DCT is partly based on the IEEE 1991 transection paper, using skew circular convolutions to achieve streamlining circuit
Platform: | Size: 25600 | Author: 李寧 | Hits:

[Compress-Decompress algrithms] 601792346200732319490634862

Description: jpeg压缩中的DCT蝶型算法verilog代码-jpeg DCT compression algorithm verilog code BUTTERFLY
Platform: | Size: 5120 | Author: wuguanying | Hits:

[VHDL-FPGA-Verilog] DCT

Description: 用verilog语言实现DCT编解码 附有DCT的说明-Using Verilog language realize DCT codec with a description of DCT
Platform: | Size: 65536 | Author: 周韧研 | Hits:

[VHDL-FPGA-Verilog] fifo8_8

Description:
Platform: | Size: 1024 | Author: 李松 | Hits:

[Other] jpeg

Description: JPEG encoder in Verilog
Platform: | Size: 41984 | Author: megkel | Hits:

[VHDL-FPGA-Verilog] JPEG2000

Description: jpeg 2000 encoder complete document
Platform: | Size: 378880 | Author: ibbu | Hits:

[VHDL-FPGA-Verilog] JPEG_Encode_verilog

Description: JPEG Encoder，JEPEG编码的Verilog代码-JPEG Encoder, JEPEG coded Verilog code
Platform: | Size: 78848 | Author: 李柏祥 | Hits:

[VHDL-FPGA-Verilog] verilog-encoder

Description: JPEG的編碼器 使用VERILOG以硬體實現 也使用MODEL模擬驗證-JPEG encoder using the VERILOG hardware implementation is also used to simulate authentication MODEL
Platform: | Size: 24576 | Author: 林曉彬 | Hits:

[Wavelet] JPEG-Encoder

Description: JPEG 编码器的verilog实现，已经在XILINX SPARTAN6上实现并验证。-The JPEG encoder verilog implementation has been implemented in a Xilinx SPARTAN6 and verify.
Platform: | Size: 39936 | Author: Justin Bieber | Hits:

[VHDL-FPGA-Verilog] JPEG

Description: JPEG Encoder Verilog Source Code
Platform: | Size: 11264 | Author: scpark | Hits:

[VHDL-FPGA-Verilog] jpeg_encoder

Description: JPEG 编码器IP核，用verilog语言编写，不支持二级采样。-JPEG Encoder IP Core,The core is written in Verilog and is designed to be portable to any target device. This core does not perform subsampling- the resulting JPEG image will have 4:4:4 subsampling
Platform: | Size: 179200 | Author: jwchen | Hits:

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