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[Embeded-SCM Developusb_jtag-20070215-1134

Description: USB JTAG 卡. 允许从主机USB口直接控制JTAG I/O 信号。 USB端与Altera USB-Blaster使用相同的协议。主机端与openwince, OpenOCD和Altera的软件兼容-USB JTAG card. From the mainframe to allow direct USB JTAG control I / O signals. USB terminal and Altera USB-Blaster use the same protocol. And the mainframe-openwince, OpenOCD and Altera software compatibility
Platform: | Size: 100302 | Author: 张森宁 | Hits:

[VHDL-FPGA-Verilogusb_jtag-20070128-1751

Description: 网上流传的usb_blaster原理图里的CPLD源码,主要是实现usb时序转换成JATG时序输出!-spreading online usb_blaster tenets of the CPLD Ituri source, usb key is timing converted into JATG sequential output!
Platform: | Size: 52224 | Author: 冯海 | Hits:

[Embeded-SCM Developusb_jtag-20070215-1134

Description: USB JTAG 卡. 允许从主机USB口直接控制JTAG I/O 信号。 USB端与Altera USB-Blaster使用相同的协议。主机端与openwince, OpenOCD和Altera的软件兼容-USB JTAG card. From the mainframe to allow direct USB JTAG control I/O signals. USB terminal and Altera USB-Blaster use the same protocol. And the mainframe-openwince, OpenOCD and Altera software compatibility
Platform: | Size: 100352 | Author: 张森宁 | Hits:

[SCMUsbBlaster

Description: 直接应用USB接口,对FPGA/CPLD等芯片的下载。便于用手提电脑的玩家使用。大家可以里面有单片机的源程序和PLD的下载程序。-Direct application of USB interface on the FPGA/CPLD chip, such as downloads. Easy to use laptop computers to use the player. Everyone can have MCU inside and PLD source of the download process.
Platform: | Size: 21504 | Author: feng | Hits:

[VHDL-FPGA-Verilogverilog_usbblaster

Description: 用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine
Platform: | Size: 1570816 | Author: 一王 | Hits:

[Embeded-SCM Developusb_blaster

Description: altera的usb下载线的制作资料,内含原理图、编程文件、文档资料等,很全的资料。-altera download of usb-line production of information, including schematics, programming files, documentation, etc., it is the whole information.
Platform: | Size: 47104 | Author: ln | Hits:

[VHDL-FPGA-Verilogjtag_logic

Description: 这是自制altera usb_blaster所用到的CPLD程序,用VHDL语言写的。
Platform: | Size: 2048 | Author: wdy2004 | Hits:

[USB developusbjtag

Description: 用于USB blaster下载线设计的JTAG仿真用的Verilog源码-For the USB blaster download cable design simulation using Verilog source JTAG
Platform: | Size: 6144 | Author: chen | Hits:

[VHDL-FPGA-Verilogusb-blaster

Description: FPGA的jtag下载线,适用于Actel系列。-FPGA-jtag download cable for Actel series.
Platform: | Size: 5030912 | Author: 小熊 | Hits:

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