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[VHDL-FPGA-Verilog终端CPLD逻辑工程文件

Description: 该工程文件实现ARM系统中CPLD的逻辑工作,起到外围资源的逻辑地址译码功能-realization of the project document ARM system CPLD logic, external resources have address decoding logic function
Platform: | Size: 117760 | Author: 王希 | Hits:

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