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[Other] leon3-memec-v2mb1000 DL : 0: LEON3 SOC GRlip IP core. Memory controller.-LEON3 GRlip SOC IP core. Memory controller.
Date : 2008-10-13 Size : 101.83kb User : 岳昆
[Other] leon3-clock-gate DL : 0: Clock gating logic for LEON3 processor.
Date : 2008-10-13 Size : 112.01kb User : 岳昆
[Other] leon3-altera-ep1c20 DL : 0: leon3 patch for altera ep1c20 FPGA.
Date : 2008-10-13 Size : 98.66kb User : 岳昆
[Other resource] leon3-altera-ep2s60-ddr DL : 0: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Date : 2008-10-13 Size : 112.09kb User : king.xia
[SourceCode] leon3 debug DL : 0: 基于leon3的debugger，采用最新的方法进行debugger的设计，是一种新的思路
Date : 2012-06-07 Size : 938byte User : 874132129@qq.com
[ARM-PowerPC-ColdFire-MIPS] leon3 DL : 0: sun公司的sparc v8处理器的配置代码。-the sun sparc ET processor configuration code.
Date : 2025-07-06 Size : 42kb User : 吴明诗
[Other] leon3-altera-ep2s60-ddr DL : 0: The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around a common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.-The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) developmen t. The IP cores are centered around a common on-c hip bus, and use a coherent method for simulation and syn thesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug
Date : 2025-07-06 Size : 101kb User : 岳昆
[Other] leon3-memec-v2mb1000 DL : 0: LEON3 SOC GRlip IP core. Memory controller.-LEON3 GRlip SOC IP core. Memory controller.
Date : 2025-07-06 Size : 102kb User : 岳昆
[Other] leon3-clock-gate DL : 0: Clock gating logic for LEON3 processor.
Date : 2025-07-06 Size : 112kb User : 岳昆
[Other] leon3-altera-ep1c20 DL : 0: leon3 patch for altera ep1c20 FPGA.
Date : 2025-07-06 Size : 99kb User : 岳昆
[Other] leon3_pci DL : 0: LEON3 SOC environment, PCI bridges.
Date : 2025-07-06 Size : 70kb User : 岳昆
[MiddleWare] leon3-altera-ep2s60-sdr DL : 0: ahb sdram interface.arm cpu series,include controller
Date : 2025-07-06 Size : 96kb User :
[VHDL-FPGA-Verilog] leon3-altera-ep2s60-ddr DL : 0: This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec
Date : 2025-07-06 Size : 112kb User :
[VHDL-FPGA-Verilog] cpu-leon3-altera-ep1c20 DL : 0: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了在Altera公司的ep1c20 FPGA的位码文件和配置文件，可以直接下载使用！-A VHDL design with the use of powerful 32-bit CPU, this document contains Altera Corporation in the ep1c20 FPGA code and configuration files, you can direct download!
Date : 2025-07-06 Size : 671kb User : zhao onely
[VHDL-FPGA-Verilog] cpu-leon3-altera-ep2s60-ddr DL : 0: 一个使用VHDL设计的具有强大功能的32位CPU，这个文件包含了与之配套的DDR控制器程序！-A VHDL design with the use of powerful 32-bit CPU, this document contains a complete set of DDR controller program!
Date : 2025-07-06 Size : 735kb User : zhao onely
[VHDL-FPGA-Verilog] cpu-leon3-xilinx-ml505 DL : 0: Date : 2025-07-06 Size : 382kb User : zhao onely
[VHDL-FPGA-Verilog] leon3 DL : 0: leon3 source code 虽然gaisler网站上有下载，但是提供此代码，希望能与更多的朋友一起学习leon-leon3 source code although gaisler website to download, but the provision of this code, would like to work with more friends with learning leon
Date : 2025-07-06 Size : 141kb User : CGF
[VHDL-FPGA-Verilog] leon3 DL : 0: 这个一个基于amba总线的leon3处理器的vhdl语言程序描述，学习fpga总线开发的请看-The amba bus-based processor vhdl language leon3 procedures described in the study developed fpga see bus
Date : 2025-07-06 Size : 2kb User : cws
[VHDL-FPGA-Verilog] LEON3 DL : 0: 基于LEON3核的在线调试工具开发基于LEON3核的在线调试工具开发-On-line debugging tools LEON3 nuclear development based on-line debugging tools LEON3 development of nuclear
Date : 2025-07-06 Size : 371kb User : 荣超群
[VHDL-FPGA-Verilog] LEON3 DL : 0: Leon3 实验指导，cpu ，讲解详细-Leon3 experimental guide, cpu, explain in detail
Date : 2025-07-06 Size : 3.39mb User : Chen Yejin

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