Search - LFSR in verilog

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[VHDL-FPGA-Verilog] LFSR DL : 0: 自动生成线形反馈移位寄存器的各种HDL源代码和原理图的工具-Automatic generation of linear feedback shift register of a variety of HDL source code and schematic tools
Update : 2025-02-17 Size : 159kb Publisher : zx
[VHDL-FPGA-Verilog] rng DL : 0: verilog编写随机数产生源程序，在硬件电路设计中应用广泛。本程序是在LFSR and a CASR 基础上实现的-random number generator to prepare Verilog source code, in the hardware circuit design applications. This procedure is in the LFSR and a CASR based on the
Update : 2025-02-17 Size : 92kb Publisher : Alex
[Crack Hack] lfsr DL : 0: 伪随机序列产生器－线性反馈移位寄存器，Verilog HDL 原代码。-Pseudo-random sequence generator- linear feedback shift register, Verilog HDL source code.
Update : 2025-02-17 Size : 1kb Publisher : 李辛
[Other] lfsr DL : 0: 用LSFR实现计数功能，可以减少对寄存器和少一个加法器，涉及verilog的人来说-Used to achieve LSFR counting functions, can be reduced to a few registers and adders, the people involved in Verilog
Update : 2025-02-17 Size : 60kb Publisher : liuzefu
[Windows Develop] LFSR DL : 0: verilog实现的8阶伪随机序列发生器，文件包含了三种主要模块：控制模块，ROM模块，线性反馈移位寄存器（LFSR）模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) module. Has passed modelsim simulation.
Update : 2025-02-17 Size : 850kb Publisher : 风影
[Other] lfsr.v.tar DL : 0: linear feedback shift register for generator in verilog code for random sequence generation.
Update : 2025-02-17 Size : 2kb Publisher : balu
[VHDL-FPGA-Verilog] BIST DL : 0: A simple BIST in VHDL. It contains a LFSR with an SISR.
Update : 2025-02-17 Size : 396kb Publisher : bommeren
[VHDL-FPGA-Verilog] ass1_2_hamming DL : 0: Hamming codes are a class of binary linear codes. They can detect up to two simultaneous bit errors, and correct single-bit errors. In particular, a single-error-correcting and double error detecting variant commonly referred to SECDED.-a) Develop a Verilog module that will generate a 7-bit encoded data from a 4-bit data. Simulate your design for two inputs. Use even or odd parity according to the least significant figure of your ID number. b) Develop a Veriog module for generating pseudorandom 4-bit data using Linear Feedback Shift Register( LFSR) method. c) Develop a Verilog module to emulate one bit error in the data transmission. This can be done by changing only one of the encoded bits at each clock cycle. You may use a ring-counter and XOr gates for doing this. This arrangement will insert error in consecutive bits at each clock cycle. d) Design a Hamming error detection and correction circuit to restore the original data. e) Compare the original data with the restored data to verify the error correction capability of your design. If the two data sets are equal an OK signal will be set.
Update : 2025-02-17 Size : 1.08mb Publisher : wei chenghao
[VHDL-FPGA-Verilog] LFSR_UPDOWN_Verilog DL : 0: the LFSR up/down counter are designed in a verilog module easy to implement in any counter operation.
Update : 2025-02-17 Size : 10kb Publisher : rajapraba
[VHDL-FPGA-Verilog] RSN DL : 0: “Randomized Smoothing Networks” introduced the idea of using networks composed of a type of comparator/memory element, initialized to random initial states, to create smoothing networks, which take arbitrary input loads into the network and produce an output that balances the load among all the outputs in a predictable manner. I created a synthesizable Verilog model of these comparator/memory elements (or “balancers”), and used a pseudo-random linear feedback shift register (LFSR) to toggle all possible initial random states for two of the proposed RSNs configurations, the Block network and the Butterfly network, verifying the results of Herlihy and Tirthapura.
Update : 2025-02-17 Size : 242kb Publisher : Stephen Bishop
[VHDL-FPGA-Verilog] LAB-16 DL : 0: 用FPGA实现的性线反馈移位寄存器（LFSR）设计。整个工程在quartusII环境下，用verilog编程。-FPGA implementation of the line feedback shift register (LFSR) design. The whole project in verilog programming the quartusII environment.
Update : 2025-02-17 Size : 297kb Publisher : 李娟
[MPI] CRC32_II DL : 0: 基于第二类LFSR串行CRC生成器的32位并行实现结构。用于SATA 3。 verilog语言。-32bit parrallel CRC module as specified in SATA 3. The module is realized with verilog.
Update : 2025-02-17 Size : 1kb Publisher : 邢博
[VHDL-FPGA-Verilog] lab2B(4)LFSR DL : 0: 实现4位二进制随机数的产生的verilog代码(Implementation of generation random 4 bits code in verilog)
Update : 2025-02-17 Size : 1kb Publisher : 电聪骑风