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[VHDL-FPGA-Verilog] library

Description: 介绍VHDL中库的调用，使对库的调用有深入的了解-VHDL introduction of library calls, so call for the Treasury have a deeper understanding of
Platform: | Size: 3072 | Author: chenwen | Hits:

[VHDL-FPGA-Verilog] DW8051_ALL

Description: 包中包括, DW8051完整的Verilog HDL代码两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: | Size: 1588224 | Author: myfingerhurt | Hits:

[VHDL-FPGA-Verilog] all_packages_20080525.tar

Description: FMF VHDL Models All the FMF models are VHDL 93 and VITAL 2000 compliant and require the VITAL 2000 library for correct compilation. They are designed for timing backannotation by means of an SDF file. The intrinsic delays default to 1 ns. We have a tool to read internal delays from an external file (in XML) and add them to the simulation through a SDF file. The most recent version is written in perl and may be downloaded from the "FMF Tools" area. Timing files are provided for over 11,500 part numbers. Also in the tools area is the document type definition (dtd) for the timing files. FMF MAKES NO WARRANTIES ON THE PERFORMANCE OF ANY MODELS IN ITS DATA REPOSITORY. USERS ARE RESPONSIBLE FOR VERIFYING THE ACCURACY OF THE MODELS, SOFTWARE OR TOOLS PROVIDED (TEST SUITES, PACKAGES, TIMING, ETC.).
Platform: | Size: 20480 | Author: ledo | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 教你在Quartus II中如何实用LPM库，对与FPGA系统设计有很好指导作用-Teach you how to Quartus II in the LPM utility library, with the FPGA system design have a very good guide
Platform: | Size: 352256 | Author: 钟桂东 | Hits:

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[VHDL-FPGA-Verilog] library

[VHDL-FPGA-Verilog] DW8051_ALL

[VHDL-FPGA-Verilog] all_packages_20080525.tar

[VHDL-FPGA-Verilog] VHDL

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