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[Other] lpc DL : 0: This document contains a specification for a new low pin count bus interface, dubbed LPC, that will be added to future Intel chip-sets. The target audience for this document are system and component designers.
Update : 2008-10-13 Size : 912.77kb Publisher : 李俊
[Other] lpcinterface DL : 0: lpc源代码verilog实现的。操作low pin count设备
Update : 2008-10-13 Size : 1.57kb Publisher : 毛军捷
[Other] lpc DL : 0: This document contains a specification for a new low pin count bus interface, dubbed LPC, that will be added to future Intel chip-sets. The target audience for this document are system and component designers.
Update : 2025-02-17 Size : 913kb Publisher : 李俊
[Other] lpcinterface DL : 0: lpc源代码verilog实现的。操作low pin count设备-LPC realize the Verilog source code. Operation of low pin count devices
Update : 2025-02-17 Size : 1kb Publisher : 毛军捷
[VHDL-FPGA-Verilog] lpc DL : 1: LPC总线从设备的verilog设计,包含状态机和中断功能。-verilog code for LPC device
Update : 2025-02-17 Size : 5kb Publisher : 饶进平
[Communication-Mobile] wb_lpc_latest.tar DL : 0: Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided. None of this has been tested (yet) with a third-party LPC Peripheral or Host.
Update : 2025-02-17 Size : 401kb Publisher : Arun
[Software Engineering] 25128901 DL : 0: Low Pin Count Interface Specification, Revision 1.1 (LPC)
Update : 2025-02-17 Size : 372kb Publisher : 张恒
[Software Engineering] lpc_lic DL : 0: This document contains a specification for a new low pin count bus interface, called LPC. The target audiences for this document are system and component designers.
Update : 2025-02-17 Size : 24kb Publisher : sungd
[Other Embeded program] Low-Pin-Count--V1.1 DL : 0: LPC标准 V1.1.PDF Low Pin Count V1.1.PDF-Low Pin Count V1.1.PDF
Update : 2025-02-17 Size : 372kb Publisher : 吴俊泉