Description: 以LVDS设计为例学习ISE中的时序分析以及低层布局器的使用方法 在底层布局器中对LVDS管脚进行约束的方法，底层布局器设计流程，底层布局器中的位置约束，时序分析器的使用方法，时序改进向导的使用等.-LVDS design for example to study the timing analysis ISE as well as the use of low-level device layout method in the bottom of the layout of LVDS device pin to bound methods, the bottom of the layout design flow, the underlying device layout position constraints, timing analyzer use timing to improve the use of the wizard. Platform: |
Size: 129024 |
Author: 程凯 |
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