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[Other] latch.rar

Description:
Platform: | Size: 1106 | Author: | Hits:

[VHDL-FPGA-Verilog] latch

Description: 门拴电路,4位选择器，alu,用verilog写的。-doors Shuan circuit, four selectors, ALU, with Verilog writes.
Platform: | Size: 1024 | Author: 杨艳 | Hits:

[VHDL-FPGA-Verilog] 16latch

Description: 16位锁存器，此程序通过quartusII软件调试通过-Latch 16, the procedure adopted quartusII software debugging
Platform: | Size: 1024 | Author: lvliangfei | Hits:

Description: 本程序实现了基于74ls373锁存器的LED显示系统的Protues仿真。实例简单明了，适合初学者，在程序基础上进行扩展。-This procedure based on the implementation of the LED latch 74ls373 Display System Simulation Protues. Examples of simple and clear, suitable for beginners, in the procedures conducted on the basis of the expansion.
Platform: | Size: 47104 | Author: 中国库 | Hits:

[VHDL-FPGA-Verilog] SR_Latch

Description: RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit is present on the output marked Q. Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R is held low, then the Q output is forced high, and stays high when S returns to low similarly, if R (Reset) is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.-RS_latch using vhdl, When using static gates as building blocks, the most fundamental latch is the simple SR latch, where S and R stand for set and reset. It can be constructed from a pair of cross-coupled NOR (Not OR) logic gates. The stored bit is present on the output marked Q. Normally, in storage mode, the S and R inputs are both low, and feedback maintains the Q and Q outputs in a constant state, with Q the complement of Q. If S (Set) is pulsed high while R is held low, then the Q output is forced high, and stays high when S returns to low similarly, if R (Reset) is pulsed high while S is held low, then the Q output is forced low, and stays low when R returns to low.
Platform: | Size: 354304 | Author: Seungyun | Hits:

[assembly language] Latch

Description: can make a latch counter by 8051
Platform: | Size: 2048 | Author: Kootlas | Hits:

[DSP program] bit4latchtest

Description: 4 bit latch for verilog prrpose helpful in verification
Platform: | Size: 138240 | Author: rahul | Hits:

[VHDL-FPGA-Verilog] latch

Description: Latch VDHL by xilinx
Platform: | Size: 268288 | Author: mohab | Hits:

[VHDL-FPGA-Verilog] D_latch

Description: actel fpga Verilog D锁存器-actel fpga Verilog D latch
Platform: | Size: 130048 | Author: zhongpeng | Hits:

[SCM] AVR-RTC-LATCH-LED-BASIC

Description: AVR RTC LATCH LED BASIC.rar
Platform: | Size: 225280 | Author: milad_m | Hits:

[VHDL-FPGA-Verilog] latch

Description: 关于闩锁效应的产生机理、触发条件、防止措施以及器件的闩锁测试的一个资料文件-This is a generation of latch-up mechanism , trigger conditions , measures and devices to prevent latch- test data file.
Platform: | Size: 195584 | Author: 袁桂毅 | Hits:

[Embeded Linux] MULTIPELEX-LATCH-LCD-C(www.bargh20.com)

Description: MULTIPELEX LATCH LCD C(www.bargh20.com)
Platform: | Size: 1419264 | Author: vahid | Hits:

[SCM] Electronic-latch

Description: 包含电子锁存器示例程序和51单片机精彩教程-Contains the electronic latch sample programs and 51 microcontroller wonderful tutorial
Platform: | Size: 1046528 | Author: sunww | Hits:

[VHDL-FPGA-Verilog] latch

Description: 频率计设计的一个模块，即锁存器，实现了对六位计数结果和溢出信号over的锁存功能 -Frequency meter design a module latch, the six count results and overflow signal over the latch function
Platform: | Size: 1024 | Author: 李雪 | Hits:

[VHDL-FPGA-Verilog] Latch

Description: 閂鎖器在FPGA的代表使用verilog HDL-Latch on behalf of the FPGA using verilog HDL
Platform: | Size: 2048 | Author: sheng | Hits:

[source in ebook] The-latch--and-triggers

Description: 锁存器和触发器区别DFGSDGDGDSSR-The latch, and triggers the difference
Platform: | Size: 68608 | Author: wkw | Hits:

[Other] latch

Description: Latch using VHDL simulated with ISIM
Platform: | Size: 1024 | Author: mehdi | Hits:

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[Other] latch.rar

[VHDL-FPGA-Verilog] latch

[VHDL-FPGA-Verilog] 16latch

[SCM] 74ls273_LED

[VHDL-FPGA-Verilog] SR_Latch

[assembly language] Latch

[DSP program] bit4latchtest

[VHDL-FPGA-Verilog] latch

[VHDL-FPGA-Verilog] D_latch

[SCM] AVR-RTC-LATCH-LED-BASIC

[VHDL-FPGA-Verilog] latch

[Embeded Linux] MULTIPELEX-LATCH-LCD-C(www.bargh20.com)

[SCM] Electronic-latch

[VHDL-FPGA-Verilog] latch

[VHDL-FPGA-Verilog] Latch

[source in ebook] The-latch--and-triggers

[Other] latch

[SCM] Four-digital-tube-dont-latch

[Other] Latch study_1

[Education soft system] lct_VC

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