Search - Lift controller VHDL

[VHDL-FPGA-Verilog] 6FloorLift

Description: 设计一个6层电梯控制器。电梯控制器是按照乘客的要求自动上、下的装置。 1、每层电梯入口处设置上下请求开关，电梯内设有顾客到达层次的停站请求开关。 2、设有电梯所处位置指示装置以及电梯运行模式（上升或者下降）指示装置。 3、电梯每秒升降一层楼。 4、电梯到达有停站请求的楼层，经过1秒电梯门打开，开门4秒后，电梯门关闭（开门指示灯灭），电梯继续运行，直至执行完最后一个请求信号后停留在当前层。 5、电梯能记忆电梯内外所有请求信号，并按照电梯运行规则按顺序响应，每个请求信号保留至有电梯响应后消除。 6、初始状态为一层开门，第一层不用向下开关，最高层不用向上开关。 7、电梯运行规则：当电梯上升时，只响应比电梯所在位置高的上楼请求信号，由下而上逐个执行，直到最后一个上楼请求执行完毕；如果高层有下楼请求，则直接升到下楼请求的最高楼层，然后进入下降模式。当电梯处于下降模式时与上升正好相反。 -design of a six-story elevator controller. Elevator Controller in accordance with the requirements of passengers automatically, the device. 1, installed on each floor elevator entrance next request switches, elevator begins to reach the level of customer stops request switch. 2, the location of elevator and escalator installations instructions operation mode (up or down) device instructions. 3, Elevator per second floor landing. 4, the lift reached a request stops floors seconds after an elevator doors open door four seconds later, elevator doors closed (to open the door to eliminate light), the continued operation of the lift, End until the implementation of the final request for a signal to stay in the current layer. 5, the lift will lift internal and external memory signal to all reques
Platform: | Size: 2048 | Author: zheng | Hits:

[Other systems] elevator

Description: 电梯控制器可实现电梯上下响应任务，到站提示音，无任务停在基站-Elevator controller can realize the lift up and down in response to mission departure and arrival tone, non-mission stopped at the base station
Platform: | Size: 1024 | Author: hilly | Hits:

[VHDL-FPGA-Verilog] lift

Description: 采用vhdl语言的电梯控制器源代码，能够实现报警，等待，并采用了标准的最优电梯运动路线。-Using VHDL language elevator controller source code, to realize the police, waiting, and the optimal use of the standard line of lift movement.
Platform: | Size: 2048 | Author: wriuwru | Hits:

[VHDL-FPGA-Verilog] Lift

Description: VHDL编写的6层电梯控制器，可在Altera的CPLD系统运行实验，内附实验报告-VHDL prepared 6-storey elevator controller in Altera s CPLD system experiment, experimental report containing
Platform: | Size: 770048 | Author: 许昕 | Hits:

[VHDL-FPGA-Verilog] lift

Description: （1）用VHDL实现四层电梯运行控制器。（2）电梯运行锁用一按钮代替（开锁上电），低电平可以运行，高电平不能运行。（3）每层电梯入口处设有上行、下行请求按钮，电梯内设有乘客到达层次的停站要求开关，高电平有效。（4）有电梯所处楼层指示灯和电梯上行、下行状态指示灯。（5）电梯到达某一层时，该层指示灯亮，并一直保持到电梯到达另一层为止。电梯上行或下行时，相应状态指示灯亮。（6）电梯接收到停站请求后，每层运行2秒，到达停站层，停留2秒后门自动打开，开门指示灯亮，开门6秒后电梯自动关门。（7）能记忆电梯内、外的请求信号，并按照电梯的运行规则依次响应，请求信号保留至响应后撤除。（8）人数超载或超重用一按钮代替，高电平有效，超载时电梯不能运行，并有相应指示。（9）事故报警按钮高电平有效，事故报警不能运行，并有指示灯，信号保留至事故消除 -(1) the realization of four-storey elevator with VHDL controller operation. (2) elevator button with a lock to run in place of (unlock power), low run, can not run high. (3) on each floor with elevator at the entrance to the uplink, downlink request button, which are equipped with passenger elevators to reach the level of the requirements of stoppings switch, high effective. (4) elevators and escalators which lights up the floor, down the state indicator. (5) elevator to reach a certain level, the level indicator light, and has remained until the elevator arrived at another level. Elevator uplink or downlink, the corresponding status indicator light. (6) Elevator stops receiving a request, each running two seconds to reach the stops layer, two seconds back door stay open automatically, open the door indicator light, 6 seconds after the elevator door closed automatically. (7) to memory elevator inside and outside the request signal, and in accordance with the rules followed
Platform: | Size: 289792 | Author: 管皮皮 | Hits:

[VHDL-FPGA-Verilog] dianti.vhd

Description: 电梯控制器的VHDL源程序很有代表性经简单修改后可用于n层控制 -Lift Controller
Platform: | Size: 5120 | Author: jimmy | Hits:

[Other Embeded program] zdsjdt

Description: 自动升降电梯控制器设计要求：设计一个6层楼的电梯控制器。该控制器可控制电梯完成6层楼的载客服而且遵循方向优先原则，并能响应提前关门延时关门，并具有超载报警和故障报警；同时指示电梯运行情况和电梯内外请求信息。-Auto-Lift elevator controller design requirements: design of a six-story elevator controller. The controller can control the completion of six-story elevator containing the principle of giving priority customer service, and follow the directions, and can respond to close ahead of schedule delay closing, and has overload alarm and fault alarm also instructed the elevator and elevator operation request information both inside and outside.
Platform: | Size: 141312 | Author: dws | Hits:

[VHDL-FPGA-Verilog] lift

Description: 设计一个八层楼房自动电梯控制器，用八个 LED显示电梯行进过程，并有数码管显示电梯当前所在楼层位置，在每层电梯入口处设有请求按钮开关，请求按钮按下则相应楼层的LED 亮。 -Design a controller, eight-story buildings, escalators, moving elevator with eight LED display process, and a digital display where the floor lift the current location of the entrance at each elevator button switch with a request, the request button is pressed the corresponding floor LED light.
Platform: | Size: 76800 | Author: zhaorongjian | Hits:

[VHDL-FPGA-Verilog] VHDL-dianti

Description: 高楼电梯自动控制系统(Windows平台上运行的ispLEVER编程软件。 ): 1统控制的电梯往返于1-9层楼。 2客要去的楼层数可手动输入并显示（设为A数）。 3梯运行的楼层数可自动显示（设为B数）。 4A>B时，系统能输出使三相电机正转的时序信号，使电梯上升；当A<B时，系统能输出使三相电机反转的时序信号，使电梯下降；当A=B时，系统能输出使三相电机停机的信号，使电梯停止运行并开门； 5是上升还是下降各层电梯门外应有指示，各层电梯门外应有使电梯上升或下降到乘客所在楼层的控制开关。注：此为word文档，但里面有源代码。-High-rise elevator control system (Windows platform programming software running on the ispLEVER. ): An elevator control system and from 1-9 floors. 2, the number of passengers going to the floor can manually enter and display (Make A number). 3 ladder run automatically display the number of floors (Set B number). 4A> B, the system can output three-phase motor is transferred to the timing signal to lift up When A <B, the system can output three-phase motor to reverse the timing signal to the lift down When A = B, the system can output a signal to shut down three-phase motor, so that the lift stops and open the door 5 is increasing or decreasing the lift on each floor outside the door should be directed, due to lift on each floor outside the elevator up or down to the floor where the passenger control switch. Note: This is a word document, but inside the source code.
Platform: | Size: 34816 | Author: | Hits:

[VHDL-FPGA-Verilog] lift

Description: 用VHDL编写的全功能四层电梯控制器-Prepared with a fully functional VHDL four elevator controller. . .
Platform: | Size: 17408 | Author: aiyun | Hits:

[VHDL-FPGA-Verilog] vikash_lift---Copy

Description: THIS THE SOURCE CODE OF LIFT CONTROLLER IN VHDL-THIS IS THE SOURCE CODE OF LIFT CONTROLLER IN VHDL
Platform: | Size: 1024 | Author: salim | Hits:

[Windows Develop] (liftzip1

Description: （1）用VHDL实现四层电梯运行控制器。（2）电梯运行锁用一按钮代替（开锁上电），低电平可以运行，高电平不能运行。（3）每层电梯入口处设有上行、下行请求按钮，电梯内设有乘客到达层次的停站要求开关，高电电平有效。（4）有电梯所处楼层指示灯和电梯上行、下行状态指示灯。（5）电梯到达某一层时，该层指示灯亮，并一直保持到电梯到达另一层为止。电梯上行或下行时，相应状态指示灯亮。（6）电梯接收到停站请求后，每层 -(1) four-story elevator run controller using VHDL. (Unlock)- (2) The operation of the lift lock with a button instead of the low you can run, can not run high. (3) on each floor elevator at the entrance has the uplink, downlink request button, elevator equipped with stops of passengers to reach the level requirements switch, high power level. (4) elevator which floor lights and elevator uplink, downlink status indicator. (5) elevator to reach a layer, the layer of light, and has remained until the elevator to reach another level. Elevator up or down, the corresponding status indicator light. (6) The elevator receives the request of the stops in each layer
Platform: | Size: 289792 | Author: thlqt | Hits:

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[VHDL-FPGA-Verilog] 6FloorLift

[Other systems] elevator

[VHDL-FPGA-Verilog] lift

[VHDL-FPGA-Verilog] Lift

[VHDL-FPGA-Verilog] lift

[VHDL-FPGA-Verilog] dianti.vhd

[Other Embeded program] zdsjdt

[VHDL-FPGA-Verilog] lift

[VHDL-FPGA-Verilog] VHDL-dianti

[VHDL-FPGA-Verilog] lift

[VHDL-FPGA-Verilog] vikash_lift---Copy

[Windows Develop] (liftzip1

[VHDL-FPGA-Verilog] assg-9-1-(lift-controller)

[VHDL-FPGA-Verilog] electric-lift-controller

[Graph program] lift

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