Description: MIPS single-cycle processor design in verilog.Instruction memory to the design and initialise it with your assembly code-a. Load the data stored in the X and Y locations of the data memory into the X and Y registers.
b. Add the X and Y registers and store the result in the Z register.
c. Store the data from the Z register into the Z memory location.
d. Load the data in the Z memory location into the T register. Platform: |
Size: 2048 |
Author:chenghao wei |
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