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[VHDL-FPGA-Verilog] daima

Description: 状态机控制AD转换模块 该模块主要实现对MAX197的控制：根据设计需要对芯片进行初始化（包括写控制字选择输入电压值范围、选择通道以及工作模式），并把通道数送指示灯显示以及用键盘控制通道号（按一下，通道号加1，同时点亮相应的指示灯，循环使用个通道）；控制状态机的工作时序，并置两次采集到的数据为12位数据输出，并经过锁存进程来锁存数据，最后从锁存器中把输出数据-The state machine controls AD and changes the module this module mainly realizes the control on MAX197: According to designing the need to initialize the chip (including writing the word of controlling and choosing to input the value range of the voltage, choose the passway and work pattern), count, give passway
Platform: | Size: 3072 | Author: 万俟斌 | Hits:

[VHDL-FPGA-Verilog] collect

Description: 用verilog编写的max197这个AD转换的程序，在ISE综合仿真均通过。-max197, verilog
Platform: | Size: 1024 | Author: liu peng | Hits:

[VHDL-FPGA-Verilog] max197

Description: FPGA实现MAX197读写程序，经过验证-FPGA control 12bAD max197
Platform: | Size: 3072 | Author: 刘义红 | Hits:

[VHDL-FPGA-Verilog] max197

Description: verilog编写的状态机控制A/D芯片MAX197正常工作-use verilog write the state machine which is used to meke the A/D chip working!
Platform: | Size: 1024 | Author: zhang | Hits:

[VHDL-FPGA-Verilog] MAX197-5STATE

Description: 使用Verilog在Quartus II下编写的MAX197 AD采集程序，系统时钟50MHz。经测试完全可使用。-Use Verilog in Quartus II prepared MAX197 AD collection procedures, the system clock 50MHz. Tested fully use.
Platform: | Size: 10849280 | Author: carlosdon | Hits:

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