Search - MAXplus2

[VHDL-FPGA-Verilog] DISPLAY-vhdl

Description: vhdl描述的显示代码 maxplus2开发环境-VHDL description of the display code development environment maxplus2
Platform: | Size: 1024 | Author: 丁智罡 | Hits:

[VHDL-FPGA-Verilog] ERFREE_COUNTER-vhdl

Description: maxplus2为开发环境 vhdl编写的自由计数器程序-maxplus2 VHDL environment for the development of free counter preparation procedures
Platform: | Size: 12288 | Author: 丁智罡 | Hits:

[VHDL-FPGA-Verilog] KEYBOARD_DEC-vhdl

Description: maxplus2为开发环境 vhdl编写的键盘程序-maxplus2 VHDL development environment for the preparation of the keyboard procedures
Platform: | Size: 1024 | Author: 丁智罡 | Hits:

[Books] max+plus ii快速入门

Description: maxplus2是一款应用于硬件编程的编程软件，本文件教你快速掌握其编程，仿真方法。-maxplus2 hardware is a programming application programming software, this document will teach you grasp its programming and simulation methods.
Platform: | Size: 344064 | Author: 刘晓飞 | Hits:

[VHDL-FPGA-Verilog] sum99

Description: 基于maxplus2的八位加法器，已经通过仿真-maxplus2 based on the eight Adder, through simulation
Platform: | Size: 1024 | Author: 海洋 | Hits:

[Communication] maxplus2

Description: 关于CPLD的文章不错的! 可以给菜菜参考下-article on the CPLD good! Can either under reference
Platform: | Size: 17325056 | Author: 许辉 | Hits:

[Program doc] edaclock

Description: maxplus2变得电子钟程序/// ///// -maxplus2 become electronic bell procedures
Platform: | Size: 683008 | Author: xuemiao | Hits:

[Other] 159357

Description: 是一个用 maxplus2做的vhdl 很平常的课程小设计 -is a maxplus2 do with vhdl very common small design courses
Platform: | Size: 11264 | Author: 李宁 | Hits:

[Other] con1

Description: maxplus2!!!!!!!!!!!!!!! 自动售货机 vhdl-vending machine VHDL maxplus2 !!!!!!!!!!!!!!!
Platform: | Size: 1024 | Author: yjk | Hits:

[VHDL-FPGA-Verilog] ram_read_write

Description: 本程序是为FPGA系统所设计的一个简单的存储和读取数据的小程序，MAXPLUS2编写-This procedure is for the FPGA system design a simple data storage and reading of small procedures, MAXPLUS2 prepared
Platform: | Size: 188416 | Author: | Hits:

[VHDL-FPGA-Verilog] chuankou_data_send

Description: 这是FPGA系统的一个简单的与上位机串行通讯的的小程序，MAXPLUS2编写-This is the FPGA system with a simple PC serial communication of small programs, MAXPLUS2 prepared
Platform: | Size: 100352 | Author: | Hits:

[VHDL-FPGA-Verilog] testled

Description: 为FPGA系统所设计的一个简单的控制LED灯显示的小程序，用MAXPLUS2编写-For the FPGA system designed to control a simple LED lights to display a small program to prepare MAXPLUS2
Platform: | Size: 68608 | Author: | Hits:

[VHDL-FPGA-Verilog] eda

Description: 来自某名牌大学电子实验室的eda指导教程，主要介绍了maxplus2，适合初学者-From a prestigious university guide EDA Electronic lab tutorials, mainly the introduction maxplus2, suitable for beginners
Platform: | Size: 484352 | Author: xiaoshuai | Hits:

[Other] MAXPLUS2

Description: EDA课程所用的Max Plus2软件，制作的半加器，有图像文件，有波形文件，建议看看，-EDA courses used by Max Plus2 software, produced a half-adder, there are image files, documents have waveform, it is recommended to see,
Platform: | Size: 31744 | Author: jimchen | Hits:

[VHDL-FPGA-Verilog] jiaotongdeng

Description: 交通灯控制系统VHDL源码，用VHDL语言、MAXPLUS2环境设计实现-VHDL core
Platform: | Size: 401408 | Author: DAVID | Hits:

[Other] maxplus2

Description: 开发VHDL的工具，MAX+PLUSII 直接下载使用,-VHDL development tools, MAX+ PLUSII direct download,
Platform: | Size: 17325056 | Author: sunruili | Hits:

[Other] maxplus2

Description: 很多初学者不知道怎么使用maxplus2，这个ppt完整并且详细的介绍了软件的功能以及使用-Many beginners do not know how to use maxplus2, this ppt complete and detailed introduction to the software functionality and the use of
Platform: | Size: 5832704 | Author: 李杜 | Hits:

[Windows Develop] shijian

Description: 基于Verilog hdl的简单的24小时时钟显示电路带有计数功能，maxplus2上运行-Based on Verilog hdl simple circuit with 24-hour clock display count function, maxplus2 run
Platform: | Size: 1024 | Author: 李洋 | Hits:

[VHDL-FPGA-Verilog] maxplus2

Description: this a good tutorial for maxplus2-this is a good tutorial for maxplus2
Platform: | Size: 605184 | Author: elahe | Hits:

[VHDL-FPGA-Verilog] Max_Plus_II-_tutorial

Description: Max+plusII(或写成Maxplus2,或MP2) 是Altera公司推出的的第三代PLD开发系统(Altera第四代PLD开发系统被称为：QuartusII，主要用于设计新器件和大规模CPLD/FPGA).使用MAX+PLUSII的设计者不需精通器件内部的复杂结构。设计者可以用自己熟悉的设计工具（如原理图输入或硬件描述语言）建立设计，MAX+PLUSII把这些设计转自动换成最终所需的格式。其设计速度非常快。Maxplus2被公认为是最易使用，人机界面最友善的PLD开发软件，特别适合初学者使用。 -Max+ plusII (or written Maxplus2, or MP2) is Altera' s third generation introduced PLD development system (Altera fourth-generation PLD development system is called: QuartusII, mainly for the design of new devices and large-scale CPLD/FPGA) . using the MAX+ PLUSII designers do not need to master the complexity of the internal structure of the device. Designers can use familiar design tools (such as schematic or hardware description language) to establish the design, MAX+ PLUSII automatically turn these designs into the final desired format. The design speed is very fast. Maxplus2 is recognized as the most easy to use, the most friendly man-machine interface PLD development software, especially for beginners.
Platform: | Size: 89088 | Author: myf | Hits:

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[VHDL-FPGA-Verilog] DISPLAY-vhdl

[VHDL-FPGA-Verilog] ERFREE_COUNTER-vhdl

[VHDL-FPGA-Verilog] KEYBOARD_DEC-vhdl

[Books] max+plus ii快速入门

[VHDL-FPGA-Verilog] sum99

[Communication] maxplus2

[Program doc] edaclock

[Other] 159357

[Other] con1

[VHDL-FPGA-Verilog] ram_read_write

[VHDL-FPGA-Verilog] chuankou_data_send

[VHDL-FPGA-Verilog] testled

[VHDL-FPGA-Verilog] eda

[Other] MAXPLUS2

[VHDL-FPGA-Verilog] jiaotongdeng

[Other] maxplus2

[Other] maxplus2

[Windows Develop] shijian

[VHDL-FPGA-Verilog] maxplus2

[VHDL-FPGA-Verilog] Max_Plus_II-_tutorial

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