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[VHDL-FPGA-Verilog] MCU_FPGA_Interface

Description: msp430单片机用IO口模拟总线时序，与FPGA进行交互的程序，附源代码，verilog，有简单文档。-msp430 I single-chip analog IO bus with timing, with the FPGA interactive process, with the source code, verilog, a simple document.
Platform: | Size: 870400 | Author: 柴佳 | Hits:

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