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[Other resource] miller

Description: miller码的matlab
Platform: | Size: 1223 | Author: 高创 | Hits:

[Other] miller

Description: 对Miller-Rabin算法的进一步改进,速度约为0.4秒验证一个素数(CPU为赛扬1.5G) //本程序使用Miller Rabin方法计算1024位素数（2进制）
Platform: | Size: 3118 | Author: 张亮 | Hits:

[JSP/Java] Miller-Rabin_primality_test_(Java)

Description: Miller-Rabin Prime Number Test
Platform: | Size: 3423 | Author: Cavin | Hits:

[Windows Develop] RSA_Robin-miller

Description: RSA_Robin-miller algorithm
Platform: | Size: 3069 | Author: liang | Hits:

[MultiLanguage] miller_rabin

Description: Miller-Rabin算法判断伪素性-Miller- Rabin Prime algorithm judgment pseudo
Platform: | Size: 1024 | Author: 胡昊 | Hits:

[matlab] miller

Description: miller码的matlab-miller code matlab
Platform: | Size: 1024 | Author: 高创 | Hits:

[Other] miller

Description: 对Miller-Rabin算法的进一步改进,速度约为0.4秒验证一个素数(CPU为赛扬1.5G) //本程序使用Miller Rabin方法计算1024位素数（2进制）-Miller-Rabin algorithm for further improvement, the rate of about 0.4 seconds to verify a prime number (CPU to Celeron 1.5G)// This procedure using Miller Rabin method 1024 primes (2 M)
Platform: | Size: 3072 | Author: 张亮 | Hits:

[JSP/Java] Miller-Rabin_primality_test_(Java)

Description: Miller-Rabin Prime Number Test
Platform: | Size: 3072 | Author: Cavin | Hits:

[Windows Develop] RSA_Robin-miller

Description: RSA_Robin-miller algorithm
Platform: | Size: 3072 | Author: liang | Hits:

[VHDL-FPGA-Verilog] miller

Description: 使用VHDL实现基带码中密勒码的编解码，并加以验证确认编解码无误-The use of VHDL code in the realization of the baseband codec Miller code, and verify the correct codec to confirm
Platform: | Size: 244736 | Author: shaw | Hits:

[Data structs] Miller-Rabin-c

Description: 求质数的算法之Miller-Rabin费马小定理-Prime number for the Miller-Rabin algorithm of Fermat' s Little Theorem
Platform: | Size: 1024 | Author: li shu | Hits:

[VHDL-FPGA-Verilog] miller

Description: 用ISE编写的VERILOG语言的米勒解码器的检测部分，检测四种解码信号。程序通过综合，但是仿真结果有点偏差，欢迎高手指点。-ISE prepared with VERILOG language detection decoder Miller of the four decoder signal detection. Procedures through an integrated, but the simulation results is biased and expert advice welcome.
Platform: | Size: 37888 | Author: kinki | Hits:

[Windows Develop] Miller-Rabin

Description: Miller-Rabin算法 随机算法 求素数-Miller-Rabin Ramdom Algorithm
Platform: | Size: 118784 | Author: zhuo | Hits:

[ELanguage] Rabin-Miller

Description: 1.Rabin-Miller算法的素性检测的原理与测试过程。 2. 有算法流程，用程序设计语言将算法过程编程实现。 3. 对输入的随机数，选择素性检测算法进行素性检测。-1.Rabin-Miller primality testing algorithm principle and the testing process. 2. There are algorithms process programming language with the process of programming the algorithm. 3. To enter the random number, select the primality testing algorithm for primality testing.
Platform: | Size: 17408 | Author: zouna | Hits:

[matlab] miller

Description: 基于Matlab的米勒编码仿真 实现RFID的Miller编码 -Miller coding to achieve
Platform: | Size: 1024 | Author: kate | Hits:

[Windows Develop] Miller-Rabin

Description: 用Witness2实现Miller-Rabin算法，主程序循环5—20次，看在100,000—200,000之间有多少个数被判为素数-With the Miller-Rabin algorithm to achieve Witness2, the main program loop 5-20 times, to see how many in number between 100,000-200,000 convicted of prime
Platform: | Size: 4096 | Author: randoll | Hits:

[Crack Hack] Miller-Rabin_primality_test_(Java)

Description: Miller rabin primality test
Platform: | Size: 3072 | Author: sihamenisas | Hits:

[VHDL-FPGA-Verilog] miller

Description: 整个系统分为两个模块：检测模块和解码模块。检测模块主要完成从输入串行序列判断出A，B或C信号，并分别输出脉冲标志脉冲串Signal_A，Signal_B和Signal_C；同时，当检测到任一信号时，BIT_EN_temp输出一个高脉冲。解码模块根据检测模块输出的三个标志脉冲进行0/1解码，输出最终的密勒解码数据DOUT；同时，输出DATA_EN和BIT_EN两个标志信号。-The whole system is divided into two modules: detection module and decoding module. Detection module of the completion of the serial sequence determine from the input A, B or C signal and the output pulse signs were pulse train Signal_A, Signal_B and Signal_C the same time, when the detection of either signal, BIT_EN_temp output a high pulse. Decoding module detection module according to the three flag pulses output 0/1 decoder, the output end of the Miller encoded data DOUT the same time, the output DATA_EN and BIT_EN two signs and signals.
Platform: | Size: 5120 | Author: zhaorongjian | Hits:

[VHDL-FPGA-Verilog] miller

Description: miller码编码模块的verilog程序，修正miller码编码模块的程序，完成miller码编码模块功能。-miller module verilog coding procedures, the amendment procedures miller coding module to complete the miller coding module function.
Platform: | Size: 2048 | Author: cy | Hits:

[Other] Miller-rabbin.py

Description: 该程序可以实现随机产生10个大数,并用miller-rabbin方法检验是否为素数.最后产生一个大素数(The program can be implemented randomly generated 10 large numbers, and miller-rabbin method is used to test whether the prime number. Finally, a large prime number)
Platform: | Size: 1024 | Author: Teen123 | Hits:
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